Intel P8700 Data Sheet - Page 76

Power/Other

Page 76 highlights

Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# VSS TRDY# RS[2]# VSS BPRI# HIT# VCCP D[3]# VSS D[9]# Power/Other Common Clock Input Common Clock Input Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/ Output Power/Other Source Synch Input/ Output Source Synch Input/ Output Power/Other Source Synch Input/ Output Power/Other Common Clock Input Common Clock Input Power/Other Common Clock Input Common Clock Input/ Output Power/Other Source Synch Input/ Output Power/Other Source Synch Input/ Output Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 D[5]# Source Synch Input/ Output VSS Power/Other ADS# Common Clock Input/ Output REQ[1]# Source Synch Input/ Output VSS Power/Other LOCK# Common Clock Input/ Output DEFER# Common Clock Input VSS Power/Other VSS Power/Other D[12]# Source Synch Input/ Output D[15]# Source Synch Input/ Output VSS Power/Other DINV[0]# Source Synch Input/ Output DSTBP[0] # Source Synch Input/ Output A[9]# Source Synch Input/ Output VSS Power/Other REQ[3]# Source Synch Input/ Output A[3]# Source Synch Input/ Output VSS Power/Other VCCP Power/Other VCCP Power/Other VSS Power/Other D[11]# Source Synch Input/ Output D[10]# Source Synch Input/ Output VSS Power/Other DSTBN[0] # Source Synch Input/ Output VSS Power/Other REQ[2]# Source Synch Input/ Output 76 Datasheet

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Package Mechanical Specifications and Pin Information
76
Datasheet
F2
VSS
Power/Other
F3
RS[0]#
Common Clock
Input
F4
RS[1]#
Common Clock
Input
F5
VSS
Power/Other
F6
RSVD
Reserved
F7
VCC
Power/Other
F8
VSS
Power/Other
F9
VCC
Power/Other
F10
VCC
Power/Other
F11
VSS
Power/Other
F12
VCC
Power/Other
F13
VSS
Power/Other
F14
VCC
Power/Other
F15
VCC
Power/Other
F16
VSS
Power/Other
F17
VCC
Power/Other
F18
VCC
Power/Other
F19
VSS
Power/Other
F20
VCC
Power/Other
F21
DRDY#
Common Clock
Input/
Output
F22
VSS
Power/Other
F23
D[4]#
Source Synch
Input/
Output
F24
D[1]#
Source Synch
Input/
Output
F25
VSS
Power/Other
F26
D[13]#
Source Synch
Input/
Output
G1
VSS
Power/Other
G2
TRDY#
Common Clock
Input
G3
RS[2]#
Common Clock
Input
G4
VSS
Power/Other
G5
BPRI#
Common Clock
Input
G6
HIT#
Common Clock
Input/
Output
G21
VCCP
Power/Other
G22
D[3]#
Source Synch
Input/
Output
G23
VSS
Power/Other
G24
D[9]#
Source Synch
Input/
Output
Table 17.
Pin # Listing
Pin #
Pin Name
Signal Buffer
Type
Directi
on
G25
D[5]#
Source Synch
Input/
Output
G26
VSS
Power/Other
H1
ADS#
Common Clock
Input/
Output
H2
REQ[1]#
Source Synch
Input/
Output
H3
VSS
Power/Other
H4
LOCK#
Common Clock
Input/
Output
H5
DEFER#
Common Clock
Input
H6
VSS
Power/Other
H21
VSS
Power/Other
H22
D[12]#
Source Synch
Input/
Output
H23
D[15]#
Source Synch
Input/
Output
H24
VSS
Power/Other
H25
DINV[0]#
Source Synch
Input/
Output
H26
DSTBP[0]
#
Source Synch
Input/
Output
J1
A[9]#
Source Synch
Input/
Output
J2
VSS
Power/Other
J3
REQ[3]#
Source Synch
Input/
Output
J4
A[3]#
Source Synch
Input/
Output
J5
VSS
Power/Other
J6
VCCP
Power/Other
J21
VCCP
Power/Other
J22
VSS
Power/Other
J23
D[11]#
Source Synch
Input/
Output
J24
D[10]#
Source Synch
Input/
Output
J25
VSS
Power/Other
J26
DSTBN[0]
#
Source Synch
Input/
Output
K1
VSS
Power/Other
K2
REQ[2]#
Source Synch
Input/
Output
Table 17.
Pin # Listing
Pin #
Pin Name
Signal Buffer
Type
Directi
on