Intel P8700 Data Sheet - Page 75
Datasheet, Power/Other, Output, BSEL[2], TEST1, TEST3, Reserved, STPCLK, Input, PWRGOOD, Open Drain
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Page 75 highlights
Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 VSS VCC VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS TEST1 TEST3 VSS VCCA VSS RSVD RSVD VSS STPCLK# PWRGOOD SLP# VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VCC VSS IERR# Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS CMOS Power/Other Test Test Power/Other Power/Other Power/Other Reserved Reserved Power/Other CMOS CMOS CMOS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Open Drain Output Output Input Input Input Output Table 17. Pin # Listing Pin # Pin Name Signal Buffer Type Directi on D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 PROCHOT # Open Drain Input/ Output RSVD Reserved VSS Power/Other DPWR# Common Clock Input/ Output TEST2 Test VSS Power/Other DBSY# Common Clock Input/ Output BNR# Common Clock Input/ Output VSS Power/Other HITM# Common Clock Input/ Output DPRSTP# CMOS Input VSS Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VCC Power/Other VSS Power/Other VCC Power/Other VSS Power/Other D[0]# Source Synch Input/ Output D[7]# Source Synch Input/ Output VSS Power/Other D[6]# Source Synch Input/ Output D[2]# Source Synch Input/ Output BR0# Common Clock Input/ Output Datasheet 75
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