Intel P8700 Data Sheet - Page 51

Datasheet

51

Package Mechanical Specifications and Pin Information

4

Package Mechanical

Specifications and Pin

Information

4.1

Package Mechanical Specifications

The processor (XE and SV) is available in 478-pin Micro-FCPGA packages as well as

479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in

Figure 9

through

Figure 13

.

The processor (POP, LV, ULV DC and ULV SC) is available 956-ball Micro-FCBGA

packages. The package mechanical dimensions are shown in

Figure 14

and

Figure 15

.

The maximum outgoing co-planarity is 0.2 mm (8 mils) for SFF processors.

The mechanical package pressure specifications are in a direction normal to the surface

of the processor. This protects the processor die from fracture risk due to uneven die

pressure distribution under tilt, stack-up tolerances and other similar conditions. These

specifications assume that a mechanical attach is designed specifically to load one type

of processor.

A 15-lbf load limit should not be exceeded on BGA packages so as to not impact solder

joint reliability after reflow. This load limit ensures that impact to the package solder

joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric

should be used

in parallel

with the 689-kPa (100 psi) pressure limit as long as neither

limits are exceeded. In some cases, designing to 15 lbf will exceed the pressure

specification of 689 kPa (100 psi) and therefore should be reduced to ensure both limits

are maintained.

Moreover, the processor package substrate should not be used as a mechanical

reference or load-bearing surface for the thermal or mechanical solution.

Caution:

The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors

are electrically conductive so care should be taken to avoid contacting the capacitors

with other electrically conductive materials on the motherboard. Doing so may short

the capacitors and possibly damage the device or render it inactive.

Section	Page
Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process	1
Revision History	6
1 Introduction	7
1.1 Terminology	8
1.2 References	9
2 Low Power Features	11
2.1 Clock Control and Low-Power States	11
2.1.1 Core Low-Power State Descriptions	13
2.1.2 Package Low-power State Descriptions	15
2.2 Enhanced Intel SpeedStep® Technology	19
2.3 Extended Low-Power States	20
2.4 FSB Low Power Enhancements	21
2.4.1 Dynamic FSB Frequency Switching	21
2.4.2 Enhanced Intel® Dynamic Acceleration Technology	22
2.5 VID-x	23
2.6 Processor Power Status Indicator (PSI-2) Signal	23
3 Electrical Specifications	25
3.1 Power and Ground Pins	25
3.2 Decoupling Guidelines	25
3.2.1 VCC Decoupling	25
3.2.2 FSB AGTL+ Decoupling	25
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking	25
3.3 Voltage Identification and Power Sequencing	26
3.4 Catastrophic Thermal Protection	29
3.5 Reserved and Unused Pins	29
3.6 FSB Frequency Select Signals (BSEL[2:0])	29
3.7 FSB Signal Groups	30
3.8 CMOS Signals	31
3.9 Maximum Ratings	31
3.10 Processor DC Specifications	32
4 Package Mechanical Specifications and Pin Information	51
4.1 Package Mechanical Specifications	51
4.2 Processor Pinout and Pin List	59
4.3 Alphabetical Signals Reference	93
5 Thermal Specifications and Design Considerations	101
5.1 Monitoring Die Temperature	108
5.1.1 Thermal Diode	108
5.1.2 Intel® Thermal Monitor	109
5.1.3 Digital Thermal Sensor	111
5.2 Out of Specification Detection	112

Intel P8700 Data Sheet - Page 51

Package Mechanical Specifications and Pin Information, 4.1 Package Mechanical Specifications

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