Intel P8700 Data Sheet - Page 12
Core Low-Power States, Grant, C1/MWAIT, C1/Auto
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Low Power Features Figure 1. Core Low-Power States C1/MWAIT Stop Grant STPCLK# asserted STPCLK# deasserted STPCLK# STPCLK# deasserted STPCLK# asserted deasserted STPCLK# asserted Core state break HLT instruction C1/Auto Halt MWAIT(C1) Halt break C0 P_LVL2 or MWAIT(C2) Core State break Core state P_LVL4 or break C2† P_LVL5/P_LVL6ø P_LVL3 or MWAIT(C4/C6) Core MWAIT(C3) C4† ‡/C6 state break C3† halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † - STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ - Core C4 state supports the package level Deep C4 sub-state. Ø - P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero. 12 Datasheet
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