Intel P8700 Data Sheet - Page 42

Intel P8700 - Core 2 Duo Processor Manual

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Electrical Specifications Table 12. Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core (5.5 W) SFF Processor Symbol IDSLP IDPRSLP IDC4 IDPWDN dICC/DT ICCA ICCP Parameter ICC Deep Sleep HFM SuperLFM ICC Deeper Sleep ICC Intel Enhanced Deeper Sleep State ICC Deep Power Down Technology State (C6) VCC Power Supply Current Slew Rate at Processor Package Pin ICC for VCCA Supply ICC for VCCP Supply before VCC Stable ICC for VCCPSupply after VCC Stable Min - - - - - - - Typ Max Unit Notes - 3.3 A 3, 4, 12 3.0 - 2.1 A 3, 4 - 1.9 A 3, 4 - 1.7 A 3, 4 - 600 mA/µs 7, 9 - 130 mA 4.5 A 10 - 2.5 A 11 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at 100 °C TJ. 4. Specified at the nominal VCC. 5. Measured at the bulk capacitors on the motherboard. 6. VCC,BOOT tolerance shown in Figure 4 and Figure 5. 7. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. 8. This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low. 9. This is a steady-state ICC current specification that is applicable when both VCCP and VCC_CORE are high. 10. Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM 11. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. 42 Datasheet

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Electrical Specifications
42
Datasheet
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across V
CC_SENSE
and V
SS_SENSE
pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M
Ω
minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 100 °C T
J
.
4.
Specified at the nominal V
CC
.
5.
Measured at the bulk capacitors on the motherboard.
6.
V
CC,BOOT
tolerance shown in
Figure 4
and
Figure 5
.
7.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal V
CC
. Not 100% tested.
8.
This is a power-up peak current specification that is applicable when V
CCP
is high and V
CC_CORE
is low.
9.
This is a steady-state I
CC
current specification that is applicable when both V
CCP
and V
CC_CORE
are high.
10.
Processor I
CC
requirements in Intel Dynamic Acceleration Technology mode are lesser than I
CC
in HFM
11.
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
I
DSLP
I
CC
Deep Sleep
HFM
SuperLFM
—
—
3.3
3.0
A
3, 4, 12
I
DPRSLP
I
CC
Deeper Sleep
—
—
2.1
A
3, 4
I
DC4
I
CC
Intel Enhanced Deeper Sleep State
—
—
1.9
A
3, 4
I
DPWDN
I
CC
Deep Power Down Technology State (C6)
—
—
1.7
A
3, 4
dI
CC/
DT
V
CC
Power Supply Current Slew Rate at Processor
Package Pin
—
—
600
mA/μs
7, 9
I
CCA
I
CC
for V
CCA
Supply
—
—
130
mA
I
CCP
I
CC
for V
CCP
Supply before V
CC
Stable
I
CC
for V
CCP
Supply after V
CC
Stable
—
—
4.5
2.5
A
A
10
11
Table 12.
Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core
(5.5 W) SFF Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes