Intel P8700 Data Sheet - Page 47
Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and, Power Optimized
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Electrical Specifications Figure 8. Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor VCC-CORE [V] VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} VCC-CORE nom {HFM|LFM} Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. 10mV= RIPPLE VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt. Error 1/ 0 ICC-CORE max {HFM|LFM} Note 1/ VCC-CORE Set Point Error Tolerance is per below: ICC-CORE [A] Tolerance VCC-CORE VID Voltage Range +/-[(VID*1.5%)-3mV] VCC-CORE > 0.7500V +/-(11.5mV-3mV) 0.5000V
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Datasheet
47
Electrical Specifications
NOTES:
1.
Applies to Low-Voltage, Ultra-Low-Voltage and Power Optimised Performance processors in
22 mmx22 mm package.
2.
Deeper Sleep mode tolerance depends on VID value.
Figure 8.
Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and
Power Optimized Performance Processor
I
CC-CORE
max
{HFM|LFM}
V
CC-CORE
[V]
V
CC-CORE
nom
{HFM|LFM}
+/-V
CC-CORE
Tolerance
= VR St. Pt. Error
1
/
V
CC-CORE, DC
min
{HFM|LFM}
V
CC-CORE, DC
max {HFM|LFM}
V
CC-CORE
max {HFM|LFM}
V
CC-CORE
min {HFM|LFM}
10mV= RIPPLE
I
CC-CORE
[A]
0
Slope = -4.0 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
Note 1
/
V
CC-CORE
Set Point Error Tolerance is per below:
Tolerance
V
CC-CORE
VID Voltage Range
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
V
CC-CORE
> 0.7500V
+/-(11.5mV-3mV)
0.5000V </= V
CC-CORE
</= 0.7500V
Total tolerance window
including ripple is +/-35mV for C6
0.3000V </= V
CC-CORE
< 0.5000V