HP Visualize J5000 hp Visualize J5000, J7000 workstations service handbook (a4 - Page 146

Processor Module PCX-T" CPU and CACHE Processor Module PCX-T" CPU and CACHE 64 64 432 PGA MASTER MEMORY CONTROLLER 39 @ 60MHz SLAVE ADDRESS BUS GSC+ INTERFACE 432 PGA U2 PDC EEPROM PDH 40 MHz GSC+ Control B Control A Slave Memory Controller 208 MQUAD Slave Memory Controller 208 MQUAD Slave Memory Controller 208 MQUAD Slave Memory Controller 208 MQUAD 16-SLOT MEMORY INTERFACE 1 GB (16 mbit DRAM) Double height SIMM Chips 4x(160 POFP) 144 @ 30 MHz 40 MHZ GSC+ GRAPHICS 3 GSC+ Card Slots 72 @ 30MHz 72b SIMM 72b SIMM Config Reg SE SCSI-2 72b SIMM 72b SIMM CORE I/O 802.3 LAN 2-PS2 RS323 Centronics 72b SIMM 72b SIMM CD-Audio 32 72b SIMM 72b SIMM 32 72b SIMM 72b SIMM 72b SIMM 72b SIMM FWSCSI EISA INTERFACE HIL RS232 8 MHz EISA 72b SIMM 72b SIMM 72b SIMM 72b SIMM SYSTEM CLOCK SOURCE System Motherboard 32 4 EISA Card Slots EISA PCA Figure 6-2. System Unit Functional Block Diagram 6-4 Diagrams