Intel 521 Data Sheet - Page 15

Datasheet

15

Electrical Specifications

2

Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1

FSB and GTLREF

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.

Platforms implement a termination voltage level for GTL+ signals defined as V

TT

. V

TT

must be

provided via a separate voltage source and not be connected to V

CC

. This configuration allows for

improved noise tolerance as processor frequency increases. Because of the speed improvements to

the data and address bus, signal integrity and platform design methods have become more critical

than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see

Table 2-18

for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to V

TT

. Intel chipsets will also provide on-die termination, thus eliminating the

need to terminate the bus on the system board for most GTL+ signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

See

Table 2-4

for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2

Power and Ground Lands

For clean on-chip power distribution, the Pentium 4 processor in the 775-land package has

226 V

CC

(power), 24 V

TT

and 273 V

SS

(ground) lands. All power lands must be connected to V

CC

,

all V

TT

lands must be connected to V

TT

, while all V

SS

lands must be connected to a system ground

plane. The processor V

CC

lands must be supplied the voltage determined by the Voltage

IDentification (VID) signals.

2.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in

Table 2-8

. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and design guidelines, refer to the

Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket

.

Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93

Intel 521 Data Sheet - Page 15

Electrical Specifications

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