Home » Intel Manuals » Processors » Intel 521 » Manual Viewer

Intel 521 Data Sheet - Page 23

Test Access Port TAP Connection, FSB Frequency Select Signals BSEL[2:0]

UPC - 683728199029

Add to My Manuals
Save this manual to your list of manuals

Page 23 highlights

Electrical Specifications 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal may be required, with each driving a different voltage level. 2.9 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-6 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency. For more information about these signals, refer to Section 4.2. Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L L L H L H H L H L H H H H L RESERVED H 133 MHz H RESERVED L 200 MHz L RESERVED H RESERVED H RESERVED L RESERVED Datasheet 23

Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93

Match case Limit results 1 per page

Datasheet

Electrical Specifications

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and

followed by any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of accepting an input

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,

and TDO. Two copies of each signal may be required, with each driving a different voltage level.

2.9

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6

defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz

FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors

will only operate at their specified FSB frequency.

For more information about these signals, refer to

Section 4.2

Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

RESERVED

133 MHz

RESERVED

200 MHz

RESERVED