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Intel 521 Data Sheet - Page 27

Table 2-9. V, Static and Transient Tolerance for 775_VR_CONFIG_04A Processors

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Electrical Specifications Table 2-9. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.70 mΩ Typical Voltage 1.75 mΩ Minimum Voltage 1.80 mΩ 0 0.000 -0.025 -0.050 5 -0.009 -0.034 -0.059 10 -0.017 -0.043 -0.068 15 -0.026 -0.051 -0.077 20 -0.034 -0.060 -0.086 25 -0.043 -0.069 -0.095 30 -0.051 -0.078 -0.104 35 -0.060 -0.086 -0.113 40 -0.068 -0.095 -0.122 45 -0.077 -0.104 -0.131 50 -0.085 -0.113 -0.140 55 -0.094 -0.121 -0.149 60 -0.102 -0.130 -0.158 65 -0.111 -0.139 -0.167 70 -0.119 -0.148 -0.176 75 -0.128 -0.156 -0.185 78 -0.133 -0.162 -0.190 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. 2. This table is intended to aid in reading discrete points on Figure 2-2. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation. Datasheet 27

Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93