Intel 521 Data Sheet - Page 86

86

Datasheet

Features

6.2.1

Normal State

This is the normal operating state for the processor.

6.2.2

HALT and Enhanced HALT Powerdown States

The Prescott processor supports the HALT or Enhanced HALT powerdown state. The Enhanced

HALT powerdown state is configured and enabled via the BIOS.

The Enhanced HALT state is a lower power state as compared to the Stop Grant State.

If Enhanced HALT is not enabled, the default powerdown state entered will be HALT. Refer to the

sections below for details about the HALT and Enhanced HALT states.

6.2.2.1

HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the HALT or

MWAIT instructions. When one of the logical processors executes the HALT instruction, that

logical processor is halted, however, the other processor continues normal operation. The processor

will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]

(NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the

Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide

for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2

Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the

logical processors executes the HALT instruction, that logical processor is halted; however, the

other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before

entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the

internal core frequency is changed. When entering the low power state, the processor will first

switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the

bus ratio back to the original value.

Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93

Intel 521 Data Sheet - Page 86

Normal State, HALT and Enhanced HALT Powerdown States - prescott

Page 86 highlights