Intel 521 Data Sheet - Page 20

20

Datasheet

Electrical Specifications

2.5

Reserved, Unused, FC and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to V

CC

, V

SS

, V

TT,

or to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See

Chapter 4

for a land listing of the processor and the

location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been included on the Pentium 4

processor in the 775-land package to allow signals to be terminated within the processor silicon.

Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the

processor silicon. However, see

Table 2-4

for details on GTL+ signals that do not include on-die

termination. Unused active high inputs should be connected through a resistor to ground (V

SS

).

Unused outputs can be left unconnected, however this may interfere with some test access port

(TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be

used when tying bidirectional signals to power or ground. When tying any signal to power or

ground, a resistor will also allow for system testability. For unused GTL+ input or I/O signals, use

pull-up resistors of the same value as the on-die termination resistors (R

TT

). Refer to

Table 2-18

for

more details.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left unconnected. Note that leaving unused outputs

unterminated may interfere with some TAP functions, complicate debug probing, and prevent

boundary scan testing.

FCx signals are signals that are available for compatibility with other processors.

The TESTHI signals must be tied to the processor V

TT

using a matched resistor, where a matched

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.

For example, if the trace impedance is 60

Ω

, then a value between 48

Ω

and 72

Ω

is required.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.

A matched resistor must be used for each group:

•

TESTHI[1:0]

•

TESTHI[7:2]

•

TESTHI8 – cannot be grouped with other TESTHI signals

•


•


•


•


•


Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93

Intel 521 Data Sheet - Page 20

Reserved, Unused, FC and TESTHI Signals

Page 20 highlights