Intel 521 Data Sheet - Page 26

26

Datasheet

Electrical Specifications

I

CC_VCCA

I

CC

FOR

PLL

LANDS

—

—

120

mA

15

I

CC_VCCIOPLL

I

CC

FOR

I/O PLL

LAND

—

—

100

mA

15

I

CC_GTLREF

I

CC

for GTLREF

—

—

200

µ

A

15

NOTES:

1.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be up-

dated with characterized data from silicon measurements at a later date.

2.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered.

Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings

within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or En-

hanced HALT State).

3.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See

Section 2.4

and

Table 2-2

for more information.

4.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth os-

cilloscope, 1.5 pF maximum probe capacitance, and 1 M

Ω

minimum impedance. The maximum length of ground wire on the probe should be less

than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

5.

Refer to

Table 2-10

and

Figure 2-3

for the minimum, typical, and maximum V

CC

allowed for a given current. The processor should not be sub-

jected to any Vcc and Icc combination wherein V

CC

exceeds V

cc_max

for a given current.

6.

775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are defined in the

Voltage Regulator Down

(VRD) 10.1 Design Guide For Desktop LGA775 Socket

.

7.

Refer to

Table 2-9

and

Figure 2-2

for the minimum, typical, and maximum V

CC

allowed for a given current. The processor should not be subjected

to any V

CC

and I

CC

combination wherein V

CC

exceeds V

CC_max

for a given current.

8.

These frequencies will operate in a system designed for 775_VR_CONFIG_04B processors. The power and I

CC

will be incrementally higher in

this configuration due to the improved loadline and resulting higher V

CC

.

9.

I

cc_max

is specified at V

CC_max

.

10.

The current specified is also for AutoHALT State.

11.

Icc Stop-Grant and I

CC

Enhanced Auto Halt are specified at V

CC_max

.

12.

The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT#

is the same as the maximum Icc for the processor.

13.

V

TT

must be provided via a separate voltage source and not be connected to V

CC

. This specification is measured at the land.

14.

Baseboard bandwidth is limited to 20 MHz.

15.

These parameters are based on design characterization and are not tested.

16.

This is maximum total current drawn from V

TT

plane by only the processor. This specification does not include the current coming from R

TT

(through the signal line). Refer to the

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket

to determine the total I

TT

drawn by the system.

Table 2-8. Voltage and Current Specifications (Sheet 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

Section	Page
Contents	3
Revision History	7
Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Packaging Terminology	12
1.2 References	13
2 Electrical Specifications	15
2.1 FSB and GTLREF	15
2.2 Power and Ground Lands	15
2.3 Decoupling Guidelines	15
2.3.1 VCC Decoupling	16
2.3.2 FSB GTL+ Decoupling	16
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking	16
2.4 Voltage Identification	17
2.4.1 Phase Lock Loop (PLL) Power and Filter	19
2.5 Reserved, Unused, FC and TESTHI Signals	20
2.6 FSB Signal Groups	21
2.7 GTL+ Asynchronous Signals	22
2.8 Test Access Port (TAP) Connection	23
2.9 FSB Frequency Select Signals (BSEL[2:0])	23
2.10 Absolute Maximum and Minimum Ratings	24
2.11 Processor DC Specifications	24
2.12 VCC Overshoot Specification	33
2.12.1 Die Voltage Validation	33
2.13 GTL+ FSB Specifications	34
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
3.9 Processor Land Coordinates	41
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	66
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	79
5.2 Processor Thermal Features	79
5.2.1 Thermal Monitor	79
5.2.2 Thermal Monitor 2	80
5.2.3 On-Demand Mode	81
5.2.4 PROCHOT# Signal	82
5.2.5 THERMTRIP# Signal	82
5.2.6 TCONTROL and Fan Speed Reduction	82
5.2.7 Thermal Diode	83
6 Features	85
6.1 Power-On Configuration Options	85
6.2 Clock Control and Low Power States	85
6.2.1 Normal State	86
6.2.2 HALT and Enhanced HALT Powerdown States	86
6.2.2.1 HALT Powerdown State	86
6.2.2.2 Enhanced HALT Powerdown State	86
6.2.3 Stop-Grant State	87
6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State	88
6.2.4.1 HALT Snoop State, Grant Snoop State	88
6.2.4.2 Enhanced HALT Snoop State	88
7 Boxed Processor Specifications	89
7.1 Mechanical Specifications	90
7.1.1 Boxed Processor Cooling Solution Dimensions	90
7.1.2 Boxed Processor Fan Heatsink Weight	91
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	91
7.2 Electrical Requirements	91
7.2.1 Fan Heatsink Power Supply	91
7.3 Thermal Specifications	93
7.3.1 Boxed Processor Cooling Requirements	93

Intel 521 Data Sheet - Page 26

Table 2-8. Voltage and Current Specifications Sheet 2 of 2

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