Intel 521 Data Sheet - Page 58

Vtt_out_left

Page 58 highlights

Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # F19 F20 F21 F22 F23 F24 F25 F26 F28 F29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 Land Name VSS D41# D43# VSS RESERVED TESTHI7 TESTHI2 TESTHI0 BCLK0 RESERVED VSS FC1 TESTHI8 TESTHI9 FC7 RESERVED DEFER# BPRI# D16# RESERVED DBI1# DSTBN1# D27# D29# D31# D32# D36# D35# DSTBP2# DSTBN2# D44# D47# RESET# TESTHI6 TESTHI3 TESTHI5 TESTHI4 BCLK1 BSEL0 BSEL2 GTLREF Signal Buffer Type Direction Power/Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Clock Input Input Input Input Power/Other Power/Other Power/Other Power/Other Source Synch Input Input Input Output Common Clock Input Common Clock Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Common Clock Input Power/Other Input Power/Other Input Power/Other Input Power/Other Input Clock Input Power/Other Output Power/Other Output Power/Other Input Table 4-2. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction H2 FC6 Power/Other Input H3 VSS Power/Other H4 RSP# Common Clock Input H5 TESTHI10 Power/Other Input H6 VSS Power/Other H7 VSS Power/Other H8 VSS Power/Other H9 VSS Power/Other H10 VSS Power/Other H11 VSS Power/Other H12 VSS Power/Other H13 VSS Power/Other H14 VSS Power/Other H15 DP1# Common Clock Input/Output H16 DP2# Common Clock Input/Output H17 VSS Power/Other H18 VSS Power/Other H19 VSS Power/Other H20 VSS Power/Other H21 VSS Power/Other H22 VSS Power/Other H23 VSS Power/Other H24 VSS Power/Other H25 VSS Power/Other H26 VSS Power/Other H27 VSS Power/Other H28 VSS Power/Other H29 GTLREF_SEL Power/Other Output H30 BSEL1 Power/Other Output J1 VTT_OUT_LEFT Power/Other Output J2 FC3 Power/Other Input J3 RESERVED J4 VSS Power/Other J5 REQ1# Source Synch Input/Output J6 REQ4# Source Synch Input/Output J7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other J10 VCC Power/Other J11 VCC Power/Other J12 VCC Power/Other 58 Datasheet

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Land Listing and Signal Descriptions
58
Datasheet
F19
VSS
Power/Other
F20
D41#
Source Synch
Input/Output
F21
D43#
Source Synch
Input/Output
F22
VSS
Power/Other
F23
RESERVED
F24
TESTHI7
Power/Other
Input
F25
TESTHI2
Power/Other
Input
F26
TESTHI0
Power/Other
Input
F28
BCLK0
Clock
Input
F29
RESERVED
G1
VSS
Power/Other
G2
FC1
Power/Other
Input
G3
TESTHI8
Power/Other
Input
G4
TESTHI9
Power/Other
Input
G5
FC7
Source Synch
Output
G6
RESERVED
G7
DEFER#
Common Clock
Input
G8
BPRI#
Common Clock
Input
G9
D16#
Source Synch
Input/Output
G10
RESERVED
G11
DBI1#
Source Synch
Input/Output
G12
DSTBN1#
Source Synch
Input/Output
G13
D27#
Source Synch
Input/Output
G14
D29#
Source Synch
Input/Output
G15
D31#
Source Synch
Input/Output
G16
D32#
Source Synch
Input/Output
G17
D36#
Source Synch
Input/Output
G18
D35#
Source Synch
Input/Output
G19
DSTBP2#
Source Synch
Input/Output
G20
DSTBN2#
Source Synch
Input/Output
G21
D44#
Source Synch
Input/Output
G22
D47#
Source Synch
Input/Output
G23
RESET#
Common Clock
Input
G24
TESTHI6
Power/Other
Input
G25
TESTHI3
Power/Other
Input
G26
TESTHI5
Power/Other
Input
G27
TESTHI4
Power/Other
Input
G28
BCLK1
Clock
Input
G29
BSEL0
Power/Other
Output
G30
BSEL2
Power/Other
Output
H1
GTLREF
Power/Other
Input
Table 4-2. Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
H2
FC6
Power/Other
Input
H3
VSS
Power/Other
H4
RSP#
Common Clock
Input
H5
TESTHI10
Power/Other
Input
H6
VSS
Power/Other
H7
VSS
Power/Other
H8
VSS
Power/Other
H9
VSS
Power/Other
H10
VSS
Power/Other
H11
VSS
Power/Other
H12
VSS
Power/Other
H13
VSS
Power/Other
H14
VSS
Power/Other
H15
DP1#
Common Clock
Input/Output
H16
DP2#
Common Clock
Input/Output
H17
VSS
Power/Other
H18
VSS
Power/Other
H19
VSS
Power/Other
H20
VSS
Power/Other
H21
VSS
Power/Other
H22
VSS
Power/Other
H23
VSS
Power/Other
H24
VSS
Power/Other
H25
VSS
Power/Other
H26
VSS
Power/Other
H27
VSS
Power/Other
H28
VSS
Power/Other
H29
GTLREF_SEL
Power/Other
Output
H30
BSEL1
Power/Other
Output
J1
VTT_OUT_LEFT
Power/Other
Output
J2
FC3
Power/Other
Input
J3
RESERVED
J4
VSS
Power/Other
J5
REQ1#
Source Synch
Input/Output
J6
REQ4#
Source Synch
Input/Output
J7
VSS
Power/Other
J8
VCC
Power/Other
J9
VCC
Power/Other
J10
VCC
Power/Other
J11
VCC
Power/Other
J12
VCC
Power/Other
Table 4-2. Numerical Land Assignment
Land
#
Land Name
Signal Buffer
Type
Direction