Intel 521 Data Sheet - Page 3

Phase Lock Loop PLL Power and Filter

Page 3 highlights

Contents Contents 1 Introduction...11 1.1 Terminology ...12 1.1.1 Processor Packaging Terminology 12 1.2 References ...13 2 Electrical Specifications ...15 2.1 FSB and GTLREF...15 2.2 Power and Ground Lands 15 2.3 Decoupling Guidelines...15 2.3.1 VCC Decoupling ...16 2.3.2 FSB GTL+ Decoupling 16 2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking 16 2.4 Voltage Identification ...17 2.4.1 Phase Lock Loop (PLL) Power and Filter 19 2.5 Reserved, Unused, FC and TESTHI Signals 20 2.6 FSB Signal Groups ...21 2.7 GTL+ Asynchronous Signals 22 2.8 Test Access Port (TAP) Connection 23 2.9 FSB Frequency Select Signals (BSEL[2:0 23 2.10 Absolute Maximum and Minimum Ratings 24 2.11 Processor DC Specifications 24 2.12 VCC Overshoot Specification 33 2.12.1 Die Voltage Validation 33 2.13 GTL+ FSB Specifications...34 3 Package Mechanical Specifications 35 3.1 Package Mechanical Drawing 35 3.2 Processor Component Keep-Out Zones 39 3.3 Package Loading Specifications 39 3.4 Package Handling Guidelines 39 3.5 Package Insertion Specifications 40 3.6 Processor Mass Specification 40 3.7 Processor Materials ...40 3.8 Processor Markings ...40 3.9 Processor Land Coordinates 41 4 Land Listing and Signal Descriptions 43 4.1 Processor Land Assignments 43 4.2 Alphabetical Signals Reference 66 5 Thermal Specifications and Design Considerations 75 5.1 Processor Thermal Specifications 75 5.1.1 Thermal Specifications 75 5.1.2 Thermal Metrology 79 5.2 Processor Thermal Features 79 5.2.1 Thermal Monitor...79 5.2.2 Thermal Monitor 2 80 Datasheet 3

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Datasheet
3
Contents
Contents
1
Introduction
....................................................................................................................................
11
1.1
Terminology
........................................................................................................................
12
1.1.1
Processor Packaging Terminology
........................................................................
12
1.2
References
.........................................................................................................................
13
2
Electrical Specifications
.................................................................................................................
15
2.1
FSB and GTLREF
...............................................................................................................
15
2.2
Power and Ground Lands
...................................................................................................
15
2.3
Decoupling Guidelines
........................................................................................................
15
2.3.1
VCC Decoupling
....................................................................................................
16
2.3.2
FSB GTL+ Decoupling
...........................................................................................
16
2.3.3
FSB Clock (BCLK[1:0]) and Processor Clocking
...................................................
16
2.4
Voltage Identification
..........................................................................................................
17
2.4.1
Phase Lock Loop (PLL) Power and Filter
..............................................................
19
2.5
Reserved, Unused, FC and TESTHI Signals
......................................................................
20
2.6
FSB Signal Groups
.............................................................................................................
21
2.7
GTL+ Asynchronous Signals
..............................................................................................
22
2.8
Test Access Port (TAP) Connection
...................................................................................
23
2.9
FSB Frequency Select Signals (BSEL[2:0])
.......................................................................
23
2.10
Absolute Maximum and Minimum Ratings
.........................................................................
24
2.11
Processor DC Specifications
..............................................................................................
24
2.12
VCC Overshoot Specification
.............................................................................................
33
2.12.1
Die Voltage Validation
...........................................................................................
33
2.13
GTL+ FSB Specifications
....................................................................................................
34
3
Package Mechanical Specifications
..............................................................................................
35
3.1
Package Mechanical Drawing
............................................................................................
35
3.2
Processor Component Keep-Out Zones
.............................................................................
39
3.3
Package Loading Specifications
.........................................................................................
39
3.4
Package Handling Guidelines
.............................................................................................
39
3.5
Package Insertion Specifications
........................................................................................
40
3.6
Processor Mass Specification
.............................................................................................
40
3.7
Processor Materials
............................................................................................................
40
3.8
Processor Markings
............................................................................................................
40
3.9
Processor Land Coordinates
..............................................................................................
41
4
Land Listing and Signal Descriptions
............................................................................................
43
4.1
Processor Land Assignments
.............................................................................................
43
4.2
Alphabetical Signals Reference
..........................................................................................
66
5
Thermal Specifications and Design Considerations
......................................................................
75
5.1
Processor Thermal Specifications
......................................................................................
75
5.1.1
Thermal Specifications
..........................................................................................
75
5.1.2
Thermal Metrology
.................................................................................................
79
5.2
Processor Thermal Features
..............................................................................................
79
5.2.1
Thermal Monitor
.....................................................................................................
79
5.2.2
Thermal Monitor 2
..................................................................................................
80