Intel E3300 Data Sheet

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  • Intel E3300 | Data Sheet - Page 1
    Intel® Celeron® Processor E3000 Series Datasheet August 2010 Document Number: 322567-003
  • Intel E3300 | Data Sheet - Page 2
    See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Celeron, Intel Core, Intel
  • Intel E3300 | Data Sheet - Page 3
    Insertion Specifications 38 3.6 Processor Mass Specification 38 3.7 Processor Materials 38 3.8 Processor Markings 38 3.9 Processor Land Coordinates 39 4 Land Listing and Signal Descriptions 41 4.1 Processor Land Assignments 41 4.2 Alphabetical Signals Reference 64 5 Thermal Specifications
  • Intel E3300 | Data Sheet - Page 4
    State 89 6.2.7 Deeper Sleep State 90 6.2.8 Enhanced Intel SpeedStep® Technology 90 6.3 Processor Power Status Indicator (PSI) Signal 90 7 Boxed Processor Specifications 91 7.1 Introduction ...91 7.2 Mechanical Specifications 92 7.2.1 Boxed Processor Cooling Solution Dimensions 92 7.2.2 Boxed
  • Intel E3300 | Data Sheet - Page 5
    3 of 3 36 9 Intel® Celeron® Processor E3000 Series Top-Side Markings Example 38 10 Processor Land Coordinates and Quadrants, Top View 39 11 land-out Diagram (Top View - Left Side 42 12 land-out Diagram (Top View - Right Side 43 13 Processor Series Thermal Profile 77 14 Case Temperature (TC
  • Intel E3300 | Data Sheet - Page 6
    54 24 Signal Description...64 25 Processor Thermal Specifications 76 26 Processor Thermal Profile 77 27 GetTemp0() Error Codes 83 28 Power-On Configuration Option Signals 85 29 Fan Heatsink Power and Signal Specifications 94 30 Fan Heatsink Power and Signal Specifications 98 6 Datasheet
  • Intel E3300 | Data Sheet - Page 7
    to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep® technology, allows tradeoffs to be made between performance and power consumption. The Intel Celeron processor E3000 series also includes the Execute Disable Bit capability. This feature, combined
  • Intel E3300 | Data Sheet - Page 8
    Revision Number 001 002 003 Description • Initial release • Intel® Celeron® processor E3400 • Changed the processor numbering from Intel Celeron processor E3x00 series to Intel Celeron processor E3000 series. • Intel® Celeron® processor E3500 Revision Date August 2009 January 2010 August 2010
  • Intel E3300 | Data Sheet - Page 9
    Intel® Core™ microarchitecture. The Intel Enhanced Core™ microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. The Intel Celeron processor E3000 series is a 64-bit processor
  • Intel E3300 | Data Sheet - Page 10
    the Intel® Celeron® processor E3000 series. • Voltage Regulator Design Guide-For this document "Voltage Regulator Design Guide" may be used in place of: - Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket • Enhanced Intel® Core™ microarchitecture
  • Intel E3300 | Data Sheet - Page 11
    , Intel® Pentium® Dual-Core Processor E6000 and E5000 Series, and Intel® Celeron Processor E3000 Series Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket LGA775 Socket Mechanical Design Guide Intel® 64 and
  • Intel E3300 | Data Sheet - Page 12
    Introduction 12 Datasheet
  • Intel E3300 | Data Sheet - Page 13
    the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information. Contact your Intel field representative for additional information. VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to
  • Intel E3300 | Data Sheet - Page 14
    speed may have different default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Celeron® Processor E3000 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the
  • Intel E3300 | Data Sheet - Page 15
    Electrical Specifications Table 2. Voltage Identification Definition VID VID VID VID VID VID VID VID 76543210 Voltage 00000000 OFF 00000010 1.6 0 0 0 0 0 1 0 0 1.5875 0 0 0 0 0 1 1 0 1.575 0 0 0 0 1 0 0 0 1.5625 00001010 1.55 0 0 0 0 1 1 0 0 1.5375 0 0 0 0 1 1 1 0 1.525 0 0 0 1 0 0 0
  • Intel E3300 | Data Sheet - Page 16
    . A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL
  • Intel E3300 | Data Sheet - Page 17
    Core voltage with respect to VSS -0.3 VTT FSB termination voltage with respect to VSS -0.3 TCASE Processor case temperature See Section 5 TSTORAGE Processor storage temperature refer to the processor case temperature specifications. 4. This rating applies to the processor and does not
  • Intel E3300 | Data Sheet - Page 18
    voltage for initial power up PLL VCC Processor Number (1 MB Cache): VCC for 775_VR_CONFIG_06: E3500 2.70 GHz E3400 2.60 GHz E3300 2.50 GHz E3200 2.40 GHz - - 5% - 1.10 1.50 - + 5% 75 - 75 75 75 V V A6 FSB termination voltage (DC + AC specifications) on Intel 3 series Chipset
  • Intel E3300 | Data Sheet - Page 19
    for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation. Datasheet 19
  • Intel E3300 | Data Sheet - Page 20
    the VID set point. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines
  • Intel E3300 | Data Sheet - Page 21
    defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
  • Intel E3300 | Data Sheet - Page 22
    Electrical Specifications 2.7.1 #/PBE#, IERR#, THERMTRIP#, TDO PROCHOT#4 BCLK[1:0], ITP_CLK[1:0]2 Power/Other VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port
  • Intel E3300 | Data Sheet - Page 23
    Specifications . Table 8. Table 9. 2.7.2 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor at least eight BCLKs for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing
  • Intel E3300 | Data Sheet - Page 24
    Table 11. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. GTL+ Signal Group DC Specifications Symbol Parameter Min
  • Intel E3300 | Data Sheet - Page 25
    mV. Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed
  • Intel E3300 | Data Sheet - Page 26
    not affect VTT min/max specifications. Refer to Table 4 for VTT specifications. 2. The leakage specification applies to powered devices on the PECI bus. + Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table
  • Intel E3300 | Data Sheet - Page 27
    NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Adjustable GTLREF circuit is used on the board (for Quad-Core processors compatibility) the two GTLREF lands
  • Intel E3300 | Data Sheet - Page 28
    signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Celeron® processor E3000 series operates at a 800 MHz FSB frequency (selected by a 200 MHz BCLK
  • Intel E3300 | Data Sheet - Page 29
    on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications. 2.8.4 BCLK[1:0] Specifications Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input
  • Intel E3300 | Data Sheet - Page 30
    : BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/nS 3 5 T6: Slew Rate Matching N/A N/A 20 % 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 200 MHz BCLK[1:0]. 2. Duty Cycle (High time/Period) must be between 40 and 60
  • Intel E3300 | Data Sheet - Page 31
    Electrical Specifications Figure 4. Measurement Points for Differential Clock Waveforms +150 mV 0.0 V -150 mV Slew_rise V_swing Slew _fall Diff T5 = BCLK[1:0] rise and fall time through the swing region +150 mV 0.0V - 150 mV § § Datasheet 31
  • Intel E3300 | Data Sheet - Page 32
    Electrical Specifications 32 Datasheet
  • Intel E3300 | Data Sheet - Page 33
    Package Mechanical Specifications 3 Package Mechanical Specifications Figure 5. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard using an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An
  • Intel E3300 | Data Sheet - Page 34
    Figure 6. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 34 Datasheet
  • Intel E3300 | Data Sheet - Page 35
    Package Mechanical Specifications Figure 7. Processor Package Drawing Sheet 2 of 3 Datasheet 35
  • Intel E3300 | Data Sheet - Page 36
    Figure 8. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 36 Datasheet
  • Intel E3300 | Data Sheet - Page 37
    package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement
  • Intel E3300 | Data Sheet - Page 38
    Markings Figure 9 shows the topside markings on the processor. This diagrams can be used to aid in the identification of the processor. Intel® Celeron® Processor E3000 Series Top-Side Markings Example INTEL ©M'06 E3300 Intel® Celeron® SLGU4 [COO] 2.50GHZ/1M/800/06 [FPO] e4 ATPO S/N 38 Datasheet
  • Intel E3300 | Data Sheet - Page 39
    Package Mechanical Specifications 3.9 Processor Land Coordinates . Figure 10. Figure 10 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V /V CC SS 30
  • Intel E3300 | Data Sheet - Page 40
    Package Mechanical Specifications 40 Datasheet
  • Intel E3300 | Data Sheet - Page 41
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 11 and Figure 12. These
  • Intel E3300 | Data Sheet - Page 42
    Land Listing and Signal Descriptions Figure 11. land-out Diagram (Top View - Left Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC
  • Intel E3300 | Data Sheet - Page 43
    Land Listing and Signal Descriptions Figure 12. land-out Diagram (Top View - Right Side) 14 VCC VCC VCC VCC VCC VCC VCC VCC VCC 13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS VSS VSS
  • Intel E3300 | Data Sheet - Page 44
    G29 Asynch CMOS Output H30 Asynch CMOS Output G30 Asynch CMOS Output A13 Power/Other Input COMP1 COMP2 COMP3 COMP8 D0# D1# D2# D3# D4# T1 Power/Other Input G2 Power/Other Input R1 Power/Other Input B13 Power/Other Input B4 Source Synch Input/Output C5 Source Synch Input/Output A4
  • Intel E3300 | Data Sheet - Page 45
    /Output Y1 Power/Other J2 F2 AK6 E24 H29 AE3 E5 F6 J3 A24 AK1 AL1 E29 G1 U1 U2 U3 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet
  • Intel E3300 | Data Sheet - Page 46
    # GTLREF0 H4 AD3 AB3 G10 AA2 AM6 C9 R3 H1 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Output Input GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 H2 Power/Other Input D4 Common Clock Input/Output E4 Common Clock
  • Intel E3300 | Data Sheet - Page 47
    VCC VCC AF22 Power/Other AF8 Power/Other AF9 Power/Other AG11 Power/Other AG12 Power/Other AG14 Power/Other AG15 Power/Other AG18 Power/Other AG19 Power/Other AG21 Power/Other AG22 Power/Other AG25 Power/Other AG26 Power/Other AG27 Power/Other AG28 Power/Other AG29 Power/Other AG30 Power/Other AG8
  • Intel E3300 | Data Sheet - Page 48
    VCC VCC VCC VCC VCC VCC VCC VCC VCC AK19 Power/Other AK21 Power/Other AK22 Power/Other AK25 Power/Other AK26 Power/Other AK8 Power/Other AK9 Power/Other AL11 Power/Other AL12 Power/Other VCC VCC VCC AL14 AL15 AL18 Power/Other Power/Other Power/Other VCC VCC VCC VCC VCC VCC AL19 AL21 AL22
  • Intel E3300 | Data Sheet - Page 49
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E3300 | Data Sheet - Page 50
    A15 A18 A2 A21 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS A6 Power/Other A9 Power/Other AA23 Power/Other VSS VSS VSS VSS VSS VSS AA24 Power/Other AA25 Power/Other AA26 Power/Other AA27 Power/Other AA28 Power/Other AA29
  • Intel E3300 | Data Sheet - Page 51
    AG13 Power/Other AG16 Power/Other AG17 Power/Other AG20 Power/Other AG23 Power/Other AG24 Power/Other AG7 Power/Other AH1 Power/Other AH10 Power/Other AH13 Power/Other AH16 Power/Other AH17 Power/Other AH20 Power/Other AH23 Power/Other AH24 Power/Other AH3 Power/Other AH6 Power/Other AH7 Power/Other
  • Intel E3300 | Data Sheet - Page 52
    D12 D15 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS VSS VSS VSS VSS VSS VSS VSS VSS D18 D21 D24 D3 D5 D6 D9 E11 E14 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS
  • Intel E3300 | Data Sheet - Page 53
    V7 W4 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E3300 | Data Sheet - Page 54
    B30 C1 C2 VSS VTT VTT VTT VTT VTT VTT DRDY# BNR# Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input/Output C3 LOCK# Common Clock Input/Output C4 VSS Power/Other C5 D01# Source Synch Input/Output C6 C7 C8 C9 C10
  • Intel E3300 | Data Sheet - Page 55
    /Output D58# Source Synch Input/Output VSS Power/Other VCCIOPLL Power/Other VSS Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other VTT Power/Other RESERVED ADS# Common Clock Input/Output VSS Power/Other HIT# Common Clock Input/Output
  • Intel E3300 | Data Sheet - Page 56
    H4 H5 H6 H7 H8 H9 H10 H11 VSS FC35 TESTHI10 VSS VSS VSS VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input H12 H13 H14 VSS VSS VSS Power/Other Power/Other Power/Other H15 H16 H17 H18 H19 H20 FC32 FC33 VSS VSS VSS VSS
  • Intel E3300 | Data Sheet - Page 57
    /Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Output Asynch CMOS Input Source Synch Input/Output Source Synch
  • Intel E3300 | Data Sheet - Page 58
    R25 R26 R27 R28 R29 R30 T1 T2 VSS VSS VSS VSS VSS VSS VSS COMP1 DPRSTP# Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input Input T3 VSS Power/Other T4 A11# Source Synch Input/Output T5 A09# Source Synch Input/Output T6 VSS
  • Intel E3300 | Data Sheet - Page 59
    Output W7 VSS Power/Other W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other Y1 FC0/ BOOTSELECT Power/Other Y2 VSS Power/Other Table 23
  • Intel E3300 | Data Sheet - Page 60
    AE17 AE18 AE19 AE20 AE21 AE22 VCC VCC VSS VSS VCC VCC VSS VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AE23 AE24 AE25 VCC VSS VSS Power/Other Power/Other Power/Other AE26 AE27 AE28 AE29 AE30 AF1 VSS VSS VSS VSS VSS TDO
  • Intel E3300 | Data Sheet - Page 61
    Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Datasheet 61
  • Intel E3300 | Data Sheet - Page 62
    AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 VCC VCC VSS VCC VCC VSS VSS VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AJ20 AJ21 AJ22 VSS VCC VCC Power/Other Power/Other Power/Other AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 VSS VSS VCC VCC VSS VSS
  • Intel E3300 | Data Sheet - Page 63
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E3300 | Data Sheet - Page 64
    bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the
  • Intel E3300 | Data Sheet - Page 65
    , then releases the bus by de-asserting BPRI#. Input/ Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be
  • Intel E3300 | Data Sheet - Page 66
    64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may
  • Intel E3300 | Data Sheet - Page 67
    low power state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Deep Sleep State enabled, refer to the Specification Update for specific processor and stepping guidance. Input/ Output DRDY# (Data Ready) is asserted by the data driver on
  • Intel E3300 | Data Sheet - Page 68
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the
  • Intel E3300 | Data Sheet - Page 69
    these signals are connected on the package to VSS. As an alternative to MSID, Intel has implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor. Refer to Section 2.5 for additional information regarding PSID. Input/ PECI is a proprietary one-wire
  • Intel E3300 | Data Sheet - Page 70
    Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications lands of all processor FSB agents. SKTOCC# (Socket Occupied) will be pulled to ground by the Output processor. System board
  • Intel E3300 | Data Sheet - Page 71
    Data Out) transfers serial test data out of the processor. Output TDO provides the serial output needed for JTAG specification support. Input The TESTHI[12,10:0] lands must be connected to the processor's appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through
  • Intel E3300 | Data Sheet - Page 72
    will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 s of the assertion of PWRGOOD (provided VTT and VCC are valid). Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools
  • Intel E3300 | Data Sheet - Page 73
    support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor are needed to support the processor voltage specification variations. See
  • Intel E3300 | Data Sheet - Page 74
    Land Listing and Signal Descriptions 74 Datasheet
  • Intel E3300 | Data Sheet - Page 75
    the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate
  • Intel E3300 | Data Sheet - Page 76
    25. Processor Thermal Specifications Processor Number Core Frequency (GHz) Thermal Design Power (W)3,4 Extended HALT Power (W)1 Deeper Sleep Power (W)2 775_VR_ CONFIG_06 Guidance5 Minimum Maximum TC (°C) TC (°C) Notes E3500 2.70 65.0 8 E3400 2.60 65.0 8 E3300 2.50 65.0 8 E3200
  • Intel E3300 | Data Sheet - Page 77
    30 32 34 36 38 40 42 44 46 Maximum Tc (°C) 55.7 56.6 57.5 58.4 59.3 60.2 61.1 62.0 62.9 63.8 64.7 65.6 Figure 13. Processor Series Thermal Profile Power 48 50 52 54 56 58 60 62 64 65 Maximum Tc (°C) 66.5 67.4 68.3 69.2 70.1 71.0 71.9 72.8 73.7 74.1 72.0 68
  • Intel E3300 | Data Sheet - Page 78
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel E3300 | Data Sheet - Page 79
    drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor
  • Intel E3300 | Data Sheet - Page 80
    to limit the processor temperature. If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption using modulation (starting and stopping) of the internal core clock, independent of
  • Intel E3300 | Data Sheet - Page 81
    must be designed to ensure the processor remains within specification. If the processor enters one of the above low-power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor DTS temperature drops below the thermal trip
  • Intel E3300 | Data Sheet - Page 82
    ) Specification. 5.3.1.1 Figure 16. TCONTROL and TCC activation on PECI-Based Systems Fan speed control solutions based on PECI use a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit
  • Intel E3300 | Data Sheet - Page 83
    Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported a default power-on condition that ensures proper processor operation during the client processor device if valid temperature readings have not
  • Intel E3300 | Data Sheet - Page 84
    Thermal Specifications and Design Considerations 84 Datasheet
  • Intel E3300 | Data Sheet - Page 85
    configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the
  • Intel E3300 | Data Sheet - Page 86
    and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT powerdown state must be configured and enabled using the BIOS for the processor to remain within specification. The Extended HALT state is a lower power state as compared to the
  • Intel E3300 | Data Sheet - Page 87
    one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT powerdown state must be enabled using the BIOS for the processor to remain within its specification. The processor will automatically
  • Intel E3300 | Data Sheet - Page 88
    , and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop. Extended Stop Grant State Extended Stop Grant is a low power state entered when
  • Intel E3300 | Data Sheet - Page 89
    while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset-based platforms with the
  • Intel E3300 | Data Sheet - Page 90
    core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Voltage/Frequency selection is software controlled by writing to processor MSR's (Model Specific Registers
  • Intel E3300 | Data Sheet - Page 91
    in millimeters and inches [in brackets]. Figure 18 shows a mechanical representation of a boxed processor. Note: Figure 18. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling
  • Intel E3300 | Data Sheet - Page 92
    Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 18 shows a mechanical representation of the boxed processor. Figure 19. Clearance is required around the fan
  • Intel E3300 | Data Sheet - Page 93
    will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 22. Baseboards must provide a matched power header to support the boxed processor. Table 29 contains specifications for the input and output signals
  • Intel E3300 | Data Sheet - Page 94
    Processor Specifications Figure 22. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power
  • Intel E3300 | Data Sheet - Page 95
    Boxed Processor Specifications Figure 23. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C 7.4 7.4.1 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. Boxed Processor Cooling Requirements
  • Intel E3300 | Data Sheet - Page 96
    Boxed Processor Specifications Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 96 Datasheet
  • Intel E3300 | Data Sheet - Page 97
    should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. Figure 26. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the
  • Intel E3300 | Data Sheet - Page 98
    Boxed Processor Specifications Table 30. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. 1
  • Intel E3300 | Data Sheet - Page 99
    use in debugging Intel Celeron® processor E3000 series systems. Tektronix and Agilent should be contacted to get specific information about their capture FSB signals. There are two sets of considerations to keep in mind when designing an Intel Celeron® processor E3000 series system that can make use
  • Intel E3300 | Data Sheet - Page 100
    Debug Tools Specifications 100 Datasheet
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Document Number: 322567-003
Intel
®
Celeron
®
Processor E3000
Series
Datasheet
August 2010