Intel E3300 Data Sheet - Page 58

Datasheet, Power/Other, PWRGOOD, Input, IGNNE, Asynch CMOS, RESERVED, DPSLP, Source Synch, Input/

Page 58 highlights

Land Listing and Signal Descriptions Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction M29 VCC Power/Other M30 N1 N2 VCC PWRGOOD IGNNE# Power/Other Power/Other Asynch CMOS Input Input N3 N4 N5 N6 N7 N8 N23 N24 N25 VSS RESERVED RESERVED VSS VSS VCC VCC VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other N26 N27 N28 N29 N30 P1 P2 P3 P4 VCC VCC VCC VCC VCC DPSLP# SMI# INIT# VSS Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Asynch CMOS Asynch CMOS Power/Other Input Input Input P5 RESERVED P6 A04# Source Synch Input/Output P7 VSS Power/Other P8 VCC Power/Other P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other P27 VSS Power/Other P28 VSS Power/Other P29 VSS Power/Other P30 VSS Power/Other R1 COMP3 Power/Other Input R2 VSS Power/Other R3 FERR#/PBE# Asynch CMOS Output R4 A08# Source Synch Input/Output R5 VSS Power/Other Table 23. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction R6 ADSTB0# Source Synch Input/Output R7 R8 R23 VSS VCC VSS Power/Other Power/Other Power/Other R24 R25 R26 R27 R28 R29 R30 T1 T2 VSS VSS VSS VSS VSS VSS VSS COMP1 DPRSTP# Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Input Input T3 VSS Power/Other T4 A11# Source Synch Input/Output T5 A09# Source Synch Input/Output T6 VSS Power/Other T7 VSS Power/Other T8 VCC Power/Other T23 VCC Power/Other T24 VCC Power/Other T25 VCC Power/Other T26 VCC Power/Other T27 VCC Power/Other T28 VCC Power/Other T29 VCC Power/Other T30 VCC Power/Other U1 FC28 Power/Other U2 FC29 Power/Other U3 FC30 Power/Other U4 A13# Source Synch Input/Output U5 A12# Source Synch Input/Output U6 A10# Source Synch Input/Output U7 VSS Power/Other U8 U23 U24 U25 U26 VCC VCC VCC VCC VCC Power/Other Power/Other Power/Other Power/Other Power/Other 58 Datasheet

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Land Listing and Signal Descriptions
58
Datasheet
M29
VCC
Power/Other
M30
VCC
Power/Other
N1
PWRGOOD
Power/Other
Input
N2
IGNNE#
Asynch CMOS
Input
N3
VSS
Power/Other
N4
RESERVED
N5
RESERVED
N6
VSS
Power/Other
N7
VSS
Power/Other
N8
VCC
Power/Other
N23
VCC
Power/Other
N24
VCC
Power/Other
N25
VCC
Power/Other
N26
VCC
Power/Other
N27
VCC
Power/Other
N28
VCC
Power/Other
N29
VCC
Power/Other
N30
VCC
Power/Other
P1
DPSLP#
Asynch CMOS
Input
P2
SMI#
Asynch CMOS
Input
P3
INIT#
Asynch CMOS
Input
P4
VSS
Power/Other
P5
RESERVED
P6
A04#
Source Synch
Input/Output
P7
VSS
Power/Other
P8
VCC
Power/Other
P23
VSS
Power/Other
P24
VSS
Power/Other
P25
VSS
Power/Other
P26
VSS
Power/Other
P27
VSS
Power/Other
P28
VSS
Power/Other
P29
VSS
Power/Other
P30
VSS
Power/Other
R1
COMP3
Power/Other
Input
R2
VSS
Power/Other
R3
FERR#/PBE#
Asynch CMOS
Output
R4
A08#
Source Synch
Input/Output
R5
VSS
Power/Other
Table 23.
Numerical Land
Assignment
Land #
Land Name
Signal Buffer
Type
Direction
R6
ADSTB0#
Source Synch
Input/Output
R7
VSS
Power/Other
R8
VCC
Power/Other
R23
VSS
Power/Other
R24
VSS
Power/Other
R25
VSS
Power/Other
R26
VSS
Power/Other
R27
VSS
Power/Other
R28
VSS
Power/Other
R29
VSS
Power/Other
R30
VSS
Power/Other
T1
COMP1
Power/Other
Input
T2
DPRSTP#
Asynch CMOS
Input
T3
VSS
Power/Other
T4
A11#
Source Synch
Input/Output
T5
A09#
Source Synch
Input/Output
T6
VSS
Power/Other
T7
VSS
Power/Other
T8
VCC
Power/Other
T23
VCC
Power/Other
T24
VCC
Power/Other
T25
VCC
Power/Other
T26
VCC
Power/Other
T27
VCC
Power/Other
T28
VCC
Power/Other
T29
VCC
Power/Other
T30
VCC
Power/Other
U1
FC28
Power/Other
U2
FC29
Power/Other
U3
FC30
Power/Other
U4
A13#
Source Synch
Input/Output
U5
A12#
Source Synch
Input/Output
U6
A10#
Source Synch
Input/Output
U7
VSS
Power/Other
U8
VCC
Power/Other
U23
VCC
Power/Other
U24
VCC
Power/Other
U25
VCC
Power/Other
U26
VCC
Power/Other
Table 23.
Numerical Land
Assignment
Land #
Land Name
Signal Buffer
Type
Direction