Intel E3300 Data Sheet - Page 46

Land Name, Signal Buffer, Direction

Page 46 highlights

Land Listing and Signal Descriptions Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC31 J16 Power/Other FC32 FC33 FC34 H15 H16 J17 Power/Other Power/Other Power/Other FC35 FC36 FC37 FC38 FC39 FC40 FC41 FERR#/PBE# GTLREF0 H4 AD3 AB3 G10 AA2 AM6 C9 R3 H1 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Output Input GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 H2 Power/Other Input D4 Common Clock Input/Output E4 Common Clock Input/Output AB2 Asynch CMOS Output N2 Asynch CMOS Input P3 Asynch CMOS Input AK3 TAP Input AJ3 TAP Input K1 Asynch CMOS Input LINT1 LOCK# MSID0 L1 Asynch CMOS Input C3 Common Clock Input/Output W1 Power/Other Output MSID1 PECI PROCHOT# PSI# PWRGOOD REQ0# V1 Power/Other Output G5 Power/Other Input/Output AL2 Asynch CMOS Input/Output Y3 Asynch CMOS Output N1 Power/Other Input K4 Source Synch Input/Output REQ1# REQ2# REQ3# J5 Source Synch Input/Output M6 Source Synch Input/Output K6 Source Synch Input/Output REQ4# RESERVED RESERVED RESERVED RESERVED J6 V2 A20 AC4 AE4 Source Synch Input/Output Table 22. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction RESERVED AE6 RESERVED RESERVED RESERVED AH2 D1 D14 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED D16 E23 E6 E7 F23 F29 G6 N4 N5 RESERVED RESET# RS0# RS1# RS2# SKTOCC# SLP# SMI# STPCLK# P5 G23 Common Clock B3 Common Clock F5 Common Clock A3 Common Clock AE8 Power/Other L2 Asynch CMOS P2 Asynch CMOS M3 Asynch CMOS Input Input Input Input Output Input Input Input TCK AE1 TAP TDI AD1 TAP TDO AF1 TAP Input Input Output TESTHI0 TESTHI1 TESTHI10 TESTHI12/ FC44 TESTHI2 F26 Power/Other W3 Power/Other H5 Power/Other W2 Power/Other F25 Power/Other Input Input Input Input Input TESTHI3 G25 Power/Other TESTHI4 G27 Power/Other TESTHI5 G26 Power/Other TESTHI6 G24 Power/Other TESTHI7 F24 Power/Other TESTHI8/FC42 G3 Power/Other TESTHI9/FC43 G4 Power/Other THERMTRIP# M2 Asynch CMOS TMS AC1 TAP Input Input Input Input Input Input Input Output Input 46 Datasheet

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100

Land Listing and Signal Descriptions
46
Datasheet
FC31
J16
Power/Other
FC32
H15
Power/Other
FC33
H16
Power/Other
FC34
J17
Power/Other
FC35
H4
Power/Other
FC36
AD3
Power/Other
FC37
AB3
Power/Other
FC38
G10
Power/Other
FC39
AA2
Power/Other
FC40
AM6
Power/Other
FC41
C9
Power/Other
FERR#/PBE#
R3
Asynch CMOS
Output
GTLREF0
H1
Power/Other
Input
GTLREF1
H2
Power/Other
Input
HIT#
D4
Common Clock
Input/Output
HITM#
E4
Common Clock
Input/Output
IERR#
AB2
Asynch CMOS
Output
IGNNE#
N2
Asynch CMOS
Input
INIT#
P3
Asynch CMOS
Input
ITP_CLK0
AK3
TAP
Input
ITP_CLK1
AJ3
TAP
Input
LINT0
K1
Asynch CMOS
Input
LINT1
L1
Asynch CMOS
Input
LOCK#
C3
Common Clock
Input/Output
MSID0
W1
Power/Other
Output
MSID1
V1
Power/Other
Output
PECI
G5
Power/Other
Input/Output
PROCHOT#
AL2
Asynch CMOS
Input/Output
PSI#
Y3
Asynch CMOS
Output
PWRGOOD
N1
Power/Other
Input
REQ0#
K4
Source Synch
Input/Output
REQ1#
J5
Source Synch
Input/Output
REQ2#
M6
Source Synch
Input/Output
REQ3#
K6
Source Synch
Input/Output
REQ4#
J6
Source Synch
Input/Output
RESERVED
V2
RESERVED
A20
RESERVED
AC4
RESERVED
AE4
Table 22.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction
RESERVED
AE6
RESERVED
AH2
RESERVED
D1
RESERVED
D14
RESERVED
D16
RESERVED
E23
RESERVED
E6
RESERVED
E7
RESERVED
F23
RESERVED
F29
RESERVED
G6
RESERVED
N4
RESERVED
N5
RESERVED
P5
RESET#
G23
Common Clock
Input
RS0#
B3
Common Clock
Input
RS1#
F5
Common Clock
Input
RS2#
A3
Common Clock
Input
SKTOCC#
AE8
Power/Other
Output
SLP#
L2
Asynch CMOS
Input
SMI#
P2
Asynch CMOS
Input
STPCLK#
M3
Asynch CMOS
Input
TCK
AE1
TAP
Input
TDI
AD1
TAP
Input
TDO
AF1
TAP
Output
TESTHI0
F26
Power/Other
Input
TESTHI1
W3
Power/Other
Input
TESTHI10
H5
Power/Other
Input
TESTHI12/
FC44
W2
Power/Other
Input
TESTHI2
F25
Power/Other
Input
TESTHI3
G25
Power/Other
Input
TESTHI4
G27
Power/Other
Input
TESTHI5
G26
Power/Other
Input
TESTHI6
G24
Power/Other
Input
TESTHI7
F24
Power/Other
Input
TESTHI8/FC42
G3
Power/Other
Input
TESTHI9/FC43
G4
Power/Other
Input
THERMTRIP#
M2
Asynch CMOS
Output
TMS
AC1
TAP
Input
Table 22.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction