Intel Q9400S Design Guidelines - Page 60
Board and System Implementation of, Intel, Quiet System Technology
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Intel® Quiet System Technology (Intel® QST) 6.2 Board and System Implementation of Intel® Quiet System Technology To implement the board must be configured as shown in Figure 21 and listed below: ME system (S0-S1) with Controller Link connected and powered DRAM with Channel A DIMM 0 installed and 2 MB reserved for Intel QST FW execution SPI Flash with sufficient space for the Intel QST Firmware SST-based thermal sensors to provide board thermal data for Intel QST algorithms Intel QST firmware Figure 21. Intel® Quiet System Technology Platform Requirements Processor Intel® (G)MCH MMEE DRAM DRAM Intel® ICH8 Controller Link FSC Control SPI SPI Flash SST Sensor Note: Simple Serial Transport (SST) is a single wire bus that is included in the ICH8 to provide additional thermal and voltage sensing capability to the Manageability Engine (ME) 60 Thermal and Mechanical Design Guidelines