SanDisk SDCFH-004G Product Manual - Page 31

Table 3-12, Attribute Memory Read Timing Specification, Common and Attribute Memory Read

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SanDisk CompactFlash Card OEM Product Manual Interface Description 3.3.6 Attribute Memory Read Timing Specification Table 3-12 contains common memory write timing specifications for all types of memory. NOTE: SanDisk CompactFlash Memory cards do not assert the -WAIT signal. Table 3-12 Attribute Memory Read Timing Specification Speed Version Item Read Cycle Time Address Access Timea Card Enable Access Time Output Enable Access Time Output Disable Time from -OE Output Enable Time from -OE Data Valid from Add Changea Address Setup Time Address Hold Time Card Enable Setup Time Card Enable Hold Time Symbol tc (R) ta (A) ta (CE) ta (OE) tdis (OE) ten (OE) tv (A) tsu (A) th (A) tsu(CE) th (CE) IEEE Symbol tAVAV tAVQV tELQV tGLQV tGHQZ tGLQNZ tAXQX tAVGL tGHAX tELGL tGHEH a. The -REG signal timing is identical to address signal timing 300 ns Min. 300 --------- 5 0 30 20 0 20 Max. --300 300 150 100 3.3.7 Memory Timing Diagrams Figure 3-3 Common and Attribute Memory Read Timing Diagram NOTE 1: Shaded areas may be high or low. © 2007 SanDisk Corporation 3-13 Rev. 12.0, 02/07

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SanDisk CompactFlash Card OEM Product Manual
Interface Description
3.3.6
Attribute Memory Read Timing Specification
Table 3-12 contains common memory write timing specifications for all types of memory.
NOTE
:
SanDisk CompactFlash Memory cards do not assert the -WAIT
signal.
Table 3-12
Attribute Memory Read Timing Specification
300 ns
Speed Version Item
Symbol
IEEE Symbol
t
c
(R)
300
Read Cycle Time
t
AVAV
t
a
(A)
300
t
AVQV
Address Access Time
a
t
a
(CE)
300
Card Enable Access Time
t
ELQV
Output Enable Access Time
t
a
(OE)
150
t
GLQV
Output Disable Time from -OE
t
dis
(OE)
100
t
GHQZ
Output Enable Time from -OE
t
en
(OE)
5
t
GLQNZ
t
v
(A)
0
t
AXQX
Data Valid from Add Change
a
Address Setup Time
t
su
(A)
30
t
AVGL
t
h
(A)
20
Address Hold Time
t
GHAX
Card Enable Setup Time
t
su
(CE)
0
t
ELGL
Card Enable Hold Time
t
h
(CE)
20
t
GHEH
Min.
Max.
a. The -REG signal timing is identical to address signal timing
3.3.7
Memory Timing Diagrams
Figure 3-3
Common and Attribute Memory Read Timing Diagram
NOTE
1:
Shaded areas may be high or low.
© 2007 SanDisk Corporation
3-13
Rev. 12.0, 02/07