Home » Fujitsu Manuals » Hard Drives » Fujitsu MPD3173AT » Manual Viewer

Fujitsu MPD3173AT Product Manual - Page 103

Ultra DMA transfer mode X

Add to My Manuals
Save this manual to your list of manuals

Page 103 highlights

At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1 1 1 1 1F6H(DH) × × × DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx xx or transfer mode [See Table 5.6] At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) × × × DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) xx xx xx xx Error information The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value. However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting. The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is posted. PIO default transfer mode PIO flow control transfer mode X Multiword DMA transfer mode X Ultra DMA transfer mode X 00000 000 (X'00') 00001 000 (X'08': Mode 0) 00001 001 (X'09': Mode 1) 00001 010 (X'0A': Mode 2) 00001 011 (X'0B': Mode 3) 00001 100 (X'0C': Mode 4) 00100 000 (X'20': Mode 0) 00100 001 (X'21': Mode 1) 00100 010 (X'22': Mode 2) 01000 000 (X'40': Mode 0) 01000 001 (X'41': Mode 1) 01000 010 (X'42': Mode 2) 01000 011 (X'43': Mode 3) 01000 100 (X'44': Mode 4) 5 - 36 C141-E069-02EN

Section	Page
Front title	1
PREFACE	4
CONTENTS	8
FIGURES	12
TABLES	14
CHAPTER 1 DEVICE OVERVIEW	16
1.1 Features	16
1.1.1 Functions and performance	16
1.1.2 Adaptability	17
1.1.3 Interface	17
1.2 Device Specifications	19
1.2.1 Specifications summary	19
1.2.2 Model and product number	20
1.3 Power Requirements	20
1.4 Environmental Specifications	23
1.5 Acoustic Noise	23
1.6 Shock and Vibration	24
1.7 Reliability	24
1.8 Error Rate	25
1.9 Media Defects	25
CHAPTER 2 DEVICE CONFIGURATION	26
2.1 Device Configuration	26
2.2 System Configuration	28
2.2.1 ATA interface	28
2.2.2 1 drive connection	28
2.2.3 2 drives connection	28
CHAPTER 3 INSTALLATION CONDITIONS	30
3.1 Dimensions	30
3.2 Mounting	32
3.3 Cable Connections	36
3.3.1 Device connector	36
3.3.2 Cable connector specifications	37
3.3.3 Device connection	37
3.3.4 Power supply connector (CN1)	38
3.3.5 System configuration for Ultra DMA	38
3.4 Jumper Settings	41
3.4.1 Location of setting jumpers	41
3.4.2 Factory default setting	42
3.4.3 Jumper configuration	42
CHAPTER 4 THEORY OF DEVICE OPERATION	46
4.1 Outline	46
4.2 Subassemblies	46
4.2.1 Disk	46
4.2.2 Head	47
4.2.3 Spindle	49
4.2.4 Actuator	49
4.2.5 Air filter	49
4.3 Circuit Configuration	50
4.4 Power-on Sequence	52
4.5 Self-calibration	54
4.5.1 Self-calibration contents	54
4.5.2 Execution timing of self-calibration	55
4.5.3 Command processing during self-calibration	55
4.6 Read/write Circuit	56
4.6.1 Read/write preamplifier (PreAMP)	56
4.6.2 Write circuit	56
4.6.3 Read circuit	58
4.6.4 Time base generator circuit	59
4.7 Servo Control	59
4.7.1 Servo control circuit	60
4.7.2 Data-surface servo format	63
4.7.3 Servo frame format	63
4.7.4 Actuator motor control	65
4.7.5 Spindle motor control	66
CHAPTER 5 INTERFACE	68
5.1 Physical Interface	69
5.1.1 Interface signals	69
5.1.2 Signal assignment on the connector	70
5.2 Logical Interface	73
5.2.1 I/O registers	73
5.2.2 Command block registers	75
5.2.3 Control block registers	80
5.3 Host Commands	80
5.3.1 Command code and parameters	81
5.3.2 Command descriptions	83
5.3.3 Error posting	133
5.4 Command Protocol	134
5.4.1 Data transferring commands from device to host	134
5.4.2 Data transferring commands from host to device	136
5.4.3 Commands without data transfer	138
5.4.4 Other commands	139
5.4.5 DMA data transfer commands	139
5.5 Ultra DMA feature set	141
5.5.1 Overview	141
5.5.2 Phases of operation	142
5.5.3 Ultra DMA data in commands	142
5.5.3.1 Initiating an Ultra DMA data in burst	142
5.5.3.2 The data in transfer	143
5.5.3.3 Pausing an Ultra DMA data in burst	143
5.5.3.4 Terminating an Ultra DMA data in burst	144
5.5.4 Ultra DMA data out commands	146
5.5.4.1 Initiating an Ultra DMA data out burst	146
5.5.4.2 The data out transfer	147
5.5.4.3 Pausing an Ultra DMA data out burst	147
5.5.4.4 Terminating an Ultra DMA data out burst	148
5.5.5 Ultra DMA CRC rules	150
5.5.6 Series termination required for Ultra DMA	151
5.6 Timing	152
5.6.1 PIO data transfer	152
5.6.2 Multiword data transfer	153
5.6.3 Ultra DMA data transfer	154
5.6.3.1 Initiating an Ultra DMA data in burst	154
5.6.3.2 Ultra DMA data burst timing requirements	155
5.6.3.3 Sustained Ultra DMA data in burst	157
5.6.3.4 Host pausing an Ultra DMA data in burst	158
5.6.3.5 Device terminating an Ultra DMA data in burst	159
5.6.3.6 Host terminating an Ultra DMA data in burst	160
5.6.3.7 Initiating an Ultra DMA data out burst	161
5.6.3.8 Sustained Ultra DMA data out burst	162
5.6.3.9 Device pausing an Ultra DMA data out burst	163
5.6.3.10 Host terminating an Ultra DMA data out burst	164
5.6.3.11 Device terminating an Ultra DMA data in burst	165
5.6.4 Power-on and reset	166
CHAPTER 6 OPERATIONS	168
6.1 Device Response to the Reset	168
6.1.1 Response to power-on	169
6.1.2 Response to hardware reset	170
6.1.3 Response to software reset	171
6.1.4 Response to diagnostic command	172
6.2 Address Translation	173
6.2.1 Default parameters	173
6.2.2 Logical address	174
6.3 Power Save	175
6.3.1 Power save mode	175
6.3.2 Power commands	177
6.4 Defect Management	177
6.4.1 Spare area	178
6.4.2 Alternating defective sectors	178
6.5 Read-Ahead Cache	180
6.5.1 Data buffer configuration	180
6.5.2 Caching operation	181
6.5.3 Usage of read segment	182
6.6 Write Cache	187
Addresses	189
Reader Comment Form	190

Match case Limit results 1 per page

C141-E069-02EN

5 - 36

At command issuance (I/O registers setting contents)

1F7

(CM)

1F6

(DH)

1F5

(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(FR)

xx or transfer mode

[See Table 5.6]

At command completion (I/O registers contents to be read)

1F7

(ST)

Status information

1F6

(DH)

1F5

(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(ER)

Error information

The host sets X'03' to the Features register.

By issuing this command with setting a value to

the Sector Count register, the transfer mode can be selected.

Upper 5 bits of the Sector Count

However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer

mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.

The IDD supports following values in the Sector Count register value.

If other value than

below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode

00000

000 (X‘00’)

PIO flow control transfer mode X

00001

000 (X‘08’:

Mode 0)

00001

001 (X‘09’:

Mode 1)

00001

010 (X‘0A’: Mode 2)

00001

011 (X‘0B’: Mode 3)

00001

100 (X‘0C’: Mode 4)

Multiword DMA transfer mode X

00100

000 (X‘20’:

Mode 0)

00100

001 (X‘21’:

Mode 1)

00100

010 (X‘22’:

Mode 2)

Ultra DMA transfer mode X

01000

000 (X‘40’:

Mode 0)

01000

001 (X‘41’:

Mode 1)

01000

010 (X‘42’:

Mode 2)

01000

011 (X‘43’:

Mode 3)

01000

100 (X‘44’:

Mode 4)