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Fujitsu MPD3173AT Product Manual - Page 147

The data out transfer, 5.4.3, Pausing an Ultra DMA data out burst

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9) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation. 11) To transfer the first word of data: the host shall negate HSTROBE no sooner than tLI after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the first word of data onto DD (15:0). 5.5.4.2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements): 1) The host shall drive a data word onto DD (15:0). 2) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode. 3) The host shall not change the state of DD (15:0) until at least tDVH after generating an HSTROBE edge to latch the data. 4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first. 5.5.4.3 Pausing an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements). a) Host pausing an Ultra DMA data out burst 1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge. Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate DDMARDY- and wait tRP before negating DMARQ. 3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge. 5 - 80 C141-E069-02EN

Section	Page
Front title	1
PREFACE	4
CONTENTS	8
FIGURES	12
TABLES	14
CHAPTER 1 DEVICE OVERVIEW	16
1.1 Features	16
1.1.1 Functions and performance	16
1.1.2 Adaptability	17
1.1.3 Interface	17
1.2 Device Specifications	19
1.2.1 Specifications summary	19
1.2.2 Model and product number	20
1.3 Power Requirements	20
1.4 Environmental Specifications	23
1.5 Acoustic Noise	23
1.6 Shock and Vibration	24
1.7 Reliability	24
1.8 Error Rate	25
1.9 Media Defects	25
CHAPTER 2 DEVICE CONFIGURATION	26
2.1 Device Configuration	26
2.2 System Configuration	28
2.2.1 ATA interface	28
2.2.2 1 drive connection	28
2.2.3 2 drives connection	28
CHAPTER 3 INSTALLATION CONDITIONS	30
3.1 Dimensions	30
3.2 Mounting	32
3.3 Cable Connections	36
3.3.1 Device connector	36
3.3.2 Cable connector specifications	37
3.3.3 Device connection	37
3.3.4 Power supply connector (CN1)	38
3.3.5 System configuration for Ultra DMA	38
3.4 Jumper Settings	41
3.4.1 Location of setting jumpers	41
3.4.2 Factory default setting	42
3.4.3 Jumper configuration	42
CHAPTER 4 THEORY OF DEVICE OPERATION	46
4.1 Outline	46
4.2 Subassemblies	46
4.2.1 Disk	46
4.2.2 Head	47
4.2.3 Spindle	49
4.2.4 Actuator	49
4.2.5 Air filter	49
4.3 Circuit Configuration	50
4.4 Power-on Sequence	52
4.5 Self-calibration	54
4.5.1 Self-calibration contents	54
4.5.2 Execution timing of self-calibration	55
4.5.3 Command processing during self-calibration	55
4.6 Read/write Circuit	56
4.6.1 Read/write preamplifier (PreAMP)	56
4.6.2 Write circuit	56
4.6.3 Read circuit	58
4.6.4 Time base generator circuit	59
4.7 Servo Control	59
4.7.1 Servo control circuit	60
4.7.2 Data-surface servo format	63
4.7.3 Servo frame format	63
4.7.4 Actuator motor control	65
4.7.5 Spindle motor control	66
CHAPTER 5 INTERFACE	68
5.1 Physical Interface	69
5.1.1 Interface signals	69
5.1.2 Signal assignment on the connector	70
5.2 Logical Interface	73
5.2.1 I/O registers	73
5.2.2 Command block registers	75
5.2.3 Control block registers	80
5.3 Host Commands	80
5.3.1 Command code and parameters	81
5.3.2 Command descriptions	83
5.3.3 Error posting	133
5.4 Command Protocol	134
5.4.1 Data transferring commands from device to host	134
5.4.2 Data transferring commands from host to device	136
5.4.3 Commands without data transfer	138
5.4.4 Other commands	139
5.4.5 DMA data transfer commands	139
5.5 Ultra DMA feature set	141
5.5.1 Overview	141
5.5.2 Phases of operation	142
5.5.3 Ultra DMA data in commands	142
5.5.3.1 Initiating an Ultra DMA data in burst	142
5.5.3.2 The data in transfer	143
5.5.3.3 Pausing an Ultra DMA data in burst	143
5.5.3.4 Terminating an Ultra DMA data in burst	144
5.5.4 Ultra DMA data out commands	146
5.5.4.1 Initiating an Ultra DMA data out burst	146
5.5.4.2 The data out transfer	147
5.5.4.3 Pausing an Ultra DMA data out burst	147
5.5.4.4 Terminating an Ultra DMA data out burst	148
5.5.5 Ultra DMA CRC rules	150
5.5.6 Series termination required for Ultra DMA	151
5.6 Timing	152
5.6.1 PIO data transfer	152
5.6.2 Multiword data transfer	153
5.6.3 Ultra DMA data transfer	154
5.6.3.1 Initiating an Ultra DMA data in burst	154
5.6.3.2 Ultra DMA data burst timing requirements	155
5.6.3.3 Sustained Ultra DMA data in burst	157
5.6.3.4 Host pausing an Ultra DMA data in burst	158
5.6.3.5 Device terminating an Ultra DMA data in burst	159
5.6.3.6 Host terminating an Ultra DMA data in burst	160
5.6.3.7 Initiating an Ultra DMA data out burst	161
5.6.3.8 Sustained Ultra DMA data out burst	162
5.6.3.9 Device pausing an Ultra DMA data out burst	163
5.6.3.10 Host terminating an Ultra DMA data out burst	164
5.6.3.11 Device terminating an Ultra DMA data in burst	165
5.6.4 Power-on and reset	166
CHAPTER 6 OPERATIONS	168
6.1 Device Response to the Reset	168
6.1.1 Response to power-on	169
6.1.2 Response to hardware reset	170
6.1.3 Response to software reset	171
6.1.4 Response to diagnostic command	172
6.2 Address Translation	173
6.2.1 Default parameters	173
6.2.2 Logical address	174
6.3 Power Save	175
6.3.1 Power save mode	175
6.3.2 Power commands	177
6.4 Defect Management	177
6.4.1 Spare area	178
6.4.2 Alternating defective sectors	178
6.5 Read-Ahead Cache	180
6.5.1 Data buffer configuration	180
6.5.2 Caching operation	181
6.5.3 Usage of read segment	182
6.6 Write Cache	187
Addresses	189
Reader Comment Form	190

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C141-E069-02EN

5 - 80

The device shall assert DDMARDY- within t

after the host has negated STOP.

After

asserting DMARQ and DDMARDY- the device shall not negate either signal until after

the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0).

This step may

occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data:

the host shall negate HSTROBE no sooner than t

after

the device has asserted DDMARDY-.

The host shall negate HSTROBE no sooner than

DVS

after the driving the first word of data onto DD (15:0).

5.5.4.2

The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically

allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):

The host shall drive a data word onto DD (15:0).

The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after

changing the state of DD (15:0).

The host shall generate an HSTROBE edge no more

frequently than t

CYC

for the selected Ultra DMA Mode.

The host shall not generate two

rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA

mode.

The host shall not change the state of DD (15:0) until at least t

DVH

after generating an

HSTROBE edge to latch the data.

The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.4.3

Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically

allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).

Host pausing an Ultra DMA data out burst

The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.

Note:

The device shall not immediately negate DMARQ to initiate Ultra DMA burst

termination when the host stops generating HSTROBE edges.

If the host does not

assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate

DDMARDY- and wait t

before negating DMARQ.

The host shall resume an Ultra DMA burst by generating an HSTROBE edge.