Intel SR1625UR Service Guide - Page 132
Chipset, Memory, Checkpoint, Diagnostic LED Decoder, Description, O=On; X=Off, Upper Nibble, PCI Bus
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Table 9. Diagnostic LED POST Code Decoder Diagnostic LED Decoder O=On; X=Off Checkpoint Upper Nibble MSB Lower Nibble LSB Description 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Chipset 0x21h X X O X X XXO Initializing a chipset component Memory 0x22h 0x23h 0x24h 0x25h 0x26h 0x27h 0x28h X X O X X X OX Reading configuration data from memory (SPD on DIMM) X X O X X X OO Detecting presence of memory X X O X X OX X Programming timing parameters in the memory controller X X O X X OX O Configuring memory parameters in the memory controller X X O X X OOX Optimizing memory controller settings X X O X X OOO Initializing memory, such as ECC init X X O X O XXX Testing memory PCI Bus 0x50h 0x51h 0x52h 0x53h 0x54h 0x55h 0x56h 0x57h X O X O X XXX Enumerating PCI buses X OX OX XXO Allocating resources to PCI buses X O X O X X OX Hot Plug PCI controller initialization X OX OX X OO Reserved for PCI bus X O X O X OX X Reserved for PCI bus X OX OX OX O Reserved for PCI bus X O X O X OOX Reserved for PCI bus X OX OX OOO Reserved for PCI bus USB 0x58h 0x59h X O X O O XXX Resetting USB bus X OX O O XXO Reserved for USB devices 114 Intel® Server System SR1625UR Service Guide