Nintendo DMG-01 Manual - Page 137
Typical timing diagram
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Game BoyTM CPU Manual 5.2. Typical timing diagram 5.2. Typical timing diagram (Based on an email from Philippe Pouliquen) The graphic shows a write followed by two reads (measured on a regular GameBoy): _________ _________ _________ ___ CLK:____/ \_________/ \_________/ \_________/ /RD:_______/ /WR: \_______/ __________ _____ _____ ___ /CS: Adr Bus:_______X X X X_ Dta: _________ _________ _________ Bus ^^^ ^ ^ ^^ Time: a b c d e fg Timing: a: 0ns this is the point at which CLK goes high, from which the other times are measured. b: 140ns point at which /RD will rise before a write. This is also the point at which the address on the address bus changes. c: 240ns point at which /CS goes low (this is pin 5 of the connector) d: 480ns point at which CLK goes low. This is also the point at which /WR goes low for a write and the GameBoy starts driving the data bus. e: 840ns by DP Page 137