Nintendo DMG-01 Manual - Page 38
Ff04 Div, Ff05 Tima
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2.13.1. I/O Registers Game BoyTM CPU Manual Bit 7 - Transfer Start Flag 0: Non transfer 1: Start transfer Bit 0 - Shift Clock 0: External Clock (500KHz Max.) 1: Internal Clock (8192Hz) Transfer is initiated by setting the Transfer Start Flag. This bit may be read and is automatically set to 0 at the end of Transfer. Transmitting and receiving serial data is done simultaneously. The received data is automatically stored in SB. 4. FF04 (DIV) Name - DIV Contents - Divider Register (R/W) This register is incremented 16384 (~16779 on SGB) times a second. Writing any value sets it to $00. 5. FF05 (TIMA) Name - TIMA Contents - Timer counter (R/W) This timer is incremented by a clock frequency specified by the TAC register ($FF07). The timer generates an interrupt when it overflows. Page 38 V 1.01