Nintendo DMG-01 Manual - Page 51

FF26 NR 52, FF30 - FF3F Wave Pattern RAM, FF40 LCDC

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Game BoyTM CPU Manual 2.13.1. I/O Registers 29. FF26 (NR 52) Name - NR 52 (Value at reset: $F1-GB, $F0-SGB) Contents - Sound on/off (R/W) Bit 7 - All sound on/off 0: stop all sound circuits 1: operate all sound circuits Bit 3 - Sound 4 ON flag Bit 2 - Sound 3 ON flag Bit 1 - Sound 2 ON flag Bit 0 - Sound 1 ON flag Bits 0 - 3 of this register are meant to be status bits to be read. Writing to these bits does NOT enable/disable sound. If your GB programs don't use sound then write $00 to this register to save 16% or more on GB power consumption. 30. FF30 - FF3F (Wave Pattern RAM) Name - Wave Pattern RAM Contents - Waveform storage for arbitrary sound data This storage area holds 32 4-bit samples that are played back upper 4 bits first. 31. FF40 (LCDC) Name - LCDC (value $91 at reset) Contents - LCD Control (R/W) Bit 7 - LCD Control Operation * by DP Page 51

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Game Boy
TM
CPU Manual
2.13.1. I/O Registers
29.
FF26 (NR 52)
Name
- NR 52
(Value at reset: $F1-GB, $F0-SGB)
Contents - Sound on/off (R/W)
Bit 7 - All sound on/off
0: stop all sound circuits
1: operate all sound circuits
Bit 3 - Sound 4 ON flag
Bit 2 - Sound 3 ON flag
Bit 1 - Sound 2 ON flag
Bit 0 - Sound 1 ON flag
Bits 0 - 3 of this register are meant to
be status bits to be read. Writing to
these bits does NOT enable/disable
sound.
If your GB programs don't use sound then
write $00 to this register to save 16%
or more on GB power consumption.
30.
FF30 - FF3F (Wave Pattern RAM)
Name
- Wave Pattern RAM
Contents - Waveform storage for arbitrary sound data
This storage area holds 32 4-bit samples
that are played back upper 4 bits first.
31.
FF40 (LCDC)
Name
- LCDC
(value $91 at reset)
Contents - LCD Control (R/W)
Bit 7 - LCD Control Operation *
by DP
Page 51