SanDisk SDSDH-1024 Product Manual - Page 109

Table 5-5, Timing Constants Definitions

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Revision 2.2 Chapter 5 - SPI Protocol SD Card Product Manual 5.23.4 Data Write The host may de-select a card (by raising the CS) at any time during the card busy period. The card will release the DataOut line one clock after the CS going high. To check if the card is still busy it needs to be re-selected by asserting (set to low) the CS signal. The card will resume busy signal (pulling DataOut low) one clock after the falling edge of CS. Device Write Timing CS Data In Data Out HL L L L L L L L L HHHL L L L NCS XHHH write command HHHH NWR HHH data block NEC NDS H H H HH H XX X H H HH Z Z H H H ******** NCR H H H card resp. H H H H H H H data response busy L Z Z Z busy H The following figure describes stop transmission operation in Multiple Block Write transfer. The "busy" may appear within NBR clocks after Stop Tran token. If there is no busy, the host may continue to the next command. Stop Transmission Timing-Multiple Block Write CS Data In L L L LL L L L L L L L L L L L L L L L L L HHH L L L L data block NW R HH H H H H H H H 1byte stop tran token NBR NEC HHH NDS XXXHHHH Data Out H H H H data resp. busy H H H H H H H H H busy L Z Z Z busy H 5.24 Timing Values Table 5-5 shows the timing values and definitions. Table 5-5 Timing Constants Definitions Value Min. Max. Unit NCS 0 --- 8 Clock cycles NCR 1 8 8 Clock cycles NRC 1 --- 8 Clock cycles NAC 1 See Note 8 Clock cycles NWR 1 --- 8 Clock cycles NEC 0 --- 8 Clock cycles NDS 0 --- 8 Clock cycles NBR 0 1 8 Clock cycles NCX 0 8 8 Clock cycles Note: The maximum read access time is calculated by the host as follows. NAC(max)= 100 ((TAAC * fPP) + (100 * NSAC)) ; fPP is the interface clock rate and TAAC & NSAC are given in the CSD Register. © 2004 SanDisk Corporation 5-19 12/08/04

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Chapter 5 – SPI Protocol
Revision 2.2
SD Card Product Manual
© 2004 SanDisk Corporation
5-19
12/08/04
5.23.4
Data Write
The host may de-select a card (by raising the CS) at any time during the card busy period.
The card will release the DataOut line one clock after the CS going high. To check if the
card is still busy it needs to be re-selected by asserting (set to low) the CS signal.
The card
will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.
Device Write Timing
The following figure describes stop transmission operation in Multiple Block Write
transfer. The “busy” may appear within N
BR
clocks after Stop Tran token.
If there is no
busy, the host may continue to the next command.
Stop Transmission Timing—Multiple Block Write
5.24
Timing Values
Table 5-5 shows the timing values and definitions.
Table 5-5
Timing Constants Definitions
Value
Min.
Max.
Unit
N
CS
0
---
8 Clock cycles
N
CR
1
8
8 Clock cycles
N
RC
1
---
8 Clock cycles
N
AC
1
See Note
8 Clock cycles
N
WR
1
---
8 Clock cycles
N
EC
0
---
8 Clock cycles
N
DS
0
---
8 Clock cycles
N
BR
0
1
8 Clock cycles
N
CX
0
8
8 Clock cycles
Note:
The maximum read access time is calculated by the host as follows.
N
AC
(max)= 100 ((TAAC * f
PP
) + (100 * NSAC)) ;
f
PP
is the interface clock rate and TAAC & NSAC are given in the CSD Register.
X
H
H
Z
Z
H
H
H
***************************************
write command
H
H
H
H
********
X
card resp.
L
Z
X
H
H
H
N
CS
N
CR
CS
Data In
Data Out
H
X
H
H
H
H
Z
Z
H
N
EC
data block
data response
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
busy
busy
H
N
WR
N
DS
H
H
H
H
L
H
H
H
Z
L
1byte
CS
Data In
Data Out
N
EC
data block
H
L
X
X
H
H
H
H
H
H
H
H
H
busy
busy
X
N
WR
N
BR
H
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
stop tran
token
Z
L
Z
data resp.
busy
H
H
H
H
H
H
H
N
DS