SanDisk SDSDH-1024 Product Manual - Page 90

Timing Values

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Revision 2.2 Chapter 4 - SD Card Protocol Description SanDisk SD Card Product Manual Stop Transmission Received after Last Data Block-Card Busy Programming Host Command NCRCycles Card Response Host Command CMD S T Content CRC E Z Z P *** P S T Content CRC E S T Content Card is Programming DAT S L L EZ Z Z Z Z Z Z Z Stop Transmission Received after Last Data Block-Card becomes Busy Host Command NCRCycles CMD S T Content CRC E Z Z P *** DAT Z Z Z Z Z Z Z Z Z Z Z S L Card Response P S T Content CRC Card is Programming Host Command E ST Content L EZ Z Z Z Z Z Z Z Erase, Set and Clear Write Protect Timing The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be erased. The erase command (CMD38), once issued, will erase all the selected write blocks. Similarly, set and clear write protect commands start a programming operation as well. The card will signal "busy" (by pulling the DAT line low) for the duration of the erase or programming operation. The bus transaction timings are the same as given for stop tran command in the "Stop Transmission Received after Last Data Block-Card Busy Programming" diagram above. Re-selecting a Busy Card When a busy card, which is currently in the dis state, is reselected it will reinstate its busy signaling on the data line. The timing diagram for this command/response/busy transaction is the same as given for stop tran command in the "Stop Transmission Received after Last Data Block-Card becomes Busy" diagram above. 4.13 Timing Values Table 4-24 defines all timing values. Table 4-24 Timing Values Value Min. Max. Unit NCR 2 64 Clock cycles NID 5 5 Clock cycles NAC 2 See Note Clock cycles NRC 8 --- Clock cycles NCC 8 --- Clock cycles NWR 2 --- Clock cycles Note-The host calculates the maximum read access time as follows: NAC(max)= 100 ((TAAC * fPP) + (100 * NSAC)) ; fPP is the interface clock rate and TAAC & NSAC are given in the CSD Register. © 2004 SanDisk Corporation 4-46 12/08/04

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Chapter 4 – SD Card Protocol Description
Revision 2.2
SanDisk SD Card Product Manual
© 2004 SanDisk Corporation
4-46
12/08/04
Stop Transmission Received after Last Data Block—Card Busy Programming
Stop Transmission Received after Last Data Block—Card becomes Busy
Erase, Set and Clear Write Protect Timing
The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be
erased. The erase command (CMD38), once issued, will erase all the selected write blocks.
Similarly, set and clear write protect commands start a programming operation as well. The
card will signal “busy” (by pulling the DAT line low) for the duration of the erase or
programming operation. The bus transaction timings are the same as given for stop tran
command in the “
Stop Transmission Received after Last Data Block—Card Busy
Programming
” diagram above.
Re-selecting a Busy Card
When a busy card, which is currently in the dis state, is reselected it will reinstate its busy
signaling on the data line. The timing diagram for this command/response/busy transaction
is the same as given for stop tran command in the “
Stop Transmission Received after Last
Data Block—Card becomes Busy
” diagram above.
4.13
Timing Values
Table 4-24 defines all timing values.
Table 4-24
Timing Values
Value
Min.
Max.
Unit
N
CR
2
64
Clock cycles
N
ID
5
5
Clock cycles
N
AC
2
See Note
Clock cycles
N
RC
8
---
Clock cycles
N
CC
8
---
Clock cycles
N
WR
2
---
Clock cycles
Note—The host calculates the maximum read access time as follows:
N
AC
(max)= 100 ((TAAC * f
PP
) + (100 * NSAC)) ;
f
PP
is the interface clock rate and TAAC & NSAC are given in the CSD Register.
CMD
DAT
S
T
Z
Z
E
S
T
Z
Z
Card Response
Z
Content
******************************************************************
Z
Z
P
S
E
Z
Z
E
Card is Programming
Host Command
Content
***
T
Content
CRC
CRC
Z
Host Command
N
CR
Cycles
S
L
L
P
CMD
S
T
DAT
Z
Z
S
T
Z
Z
Card Response
Z
Content
*********************
Z
Z
S
E
Z
Z
E
Card is Programming
Host Command
Content
P
T
Content
CRC
CRC
Z
Host Command
N
CR
Cycles
Z
Z
Z
Z
Z
Z
S
Z
Z
Z
L
Z
Z
L
***
E
P