Xerox 4540 Service Manual - Page 199

B A P P E N D I X BIOS POST Codes This appendix describes the BIOS POST Codes. It contains the following sections: ■ Section B.1, "Introduction to Power-On Self-Test (POST)" on page B-1 ■ Section B.2, "How to Load Optimal Default Settings During BIOS/POST" on page B-2 ■ Section B.3, "How BIOS POST Memory Testing Works" on page B-2 ■ Section B.4, "Redirecting Console Output" on page B-3 ■ Section B.5, "Changing POST Options" on page B-4 ■ Section B.6, "POST Codes" on page B-6 ■ Section B.7, "POST Code Checkpoints" on page B-8 B.1 Introduction to Power-On Self-Test (POST) The system BIOS provides a rudimentary power-on self-test. The basic devices required for the server to operate are checked, memory is tested, the Marvell disk controller (X4500), or the LSI SAS1068E disk controller (X4540), and the attached disks in slot 0 and slot 1 are probed and enumerated, and the two Intel Gigabit Ethernet controllers are initialized. The progress of the self-test is indicated by a series of POST codes. These codes are displayed at the lower-right hand corner of the system's VGA screen (once the selftest has progressed far enough to initialize the video monitor). However, the codes are displayed as the self-test runs and scroll off the screen too quickly to be read. An alternate method of displaying the POST codes is to redirect the output of the console to a serial port (see Section B.4, "Redirecting Console Output" on page B-3). The message BMC Responding is displayed at the end of POST. B-1