Home » Xerox Manuals » Scanners » Xerox 4540 » Manual Viewer

Xerox 4540 Service Manual - Page 204

B.6 POST Codes, secondary I/O port 81. In the POST codes listed

Add to My Manuals
Save this manual to your list of manuals

Page 204 highlights

B.6 POST Codes TABLE B-2 contains descriptions of each of the POST codes, listed in the same order in which they are generated. These POST codes appear as a four-digit string that is a combination of two-digit output from primary I/O port 80 and two-digit output from secondary I/O port 81. In the POST codes listed in TABLE B-2, the first two digits are from port 81 and the last two digits are from port 80. TABLE B-2 POST Codes Post Code 00d0 00d1 00d2 00d3 01d4 01d5 01d6 01d7 01d8 01d9 01da 0004 00c2 00c3 00c5 00c6 00c7 000a 000c Description Coming out of POR, PCI configuration space initialization, enabling 8111's SMBus. Keyboard controller BAT, waking up from PM, saving power-on CPUID in scratch CMOS. Disable cache, full memory sizing, and verify that flat mode is enabled. Memory detections and sizing in boot block, cache disabled, IO APIC enabled. Test base 512 KB memory. Adjust policies and cache first 8MB. Boot block code is copied from ROM to lower RAM. BIOS is now executing out of RAM. Key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested. Restoring CPUID; moving boot block-runtime interface module to RAM; determine whether to execute serial flash. Decompressing runtime module into RAM. Storing CPUID information in memory. Copying main BIOS into memory. Giving control to BIOS POST. Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. If the CMOS checksum is bad, update CMOS with power-on default values. Set up boot strap processor for POST. This includes frequency calculation, loading BSP microcode, and applying user requested value for GART Error Reporting setup question. Errata workarounds applied to the BSP (#78 & #110). Enumerate and set up application processors. This includes microcode loading, and workarounds for errata (#78, #110, #106, #107, #69, #63). Reenable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. HT sets link frequencies and widths to their final values. Initializing the 8042 compatible Keyboard Controller. Detecting the presence of keyboard in KBC port. B-6 Sun Fire X4500/X4540 Server Service Manual • May 2010

Section	Page
Sun Fire X4500/X4540 Server Service Manual	1
Contents	3
Preface	13
Introduction to the Sun Fire X4500 and X4540 Servers	15
1.1 Features of the Sun Fire X4500	15
1.1.1 System Configurations (X4500)	16
1.1.2 Standard I/O (X4500)	16
1.1.3 Summary of Features (X4500)	17
1.2 Features of the Sun Fire X4540	18
1.2.1 System Configurations (X4540)	18
1.2.2 Standard I/O (X4540)	18
1.2.3 Summary of Features (X4540)	19
1.3 Exterior Features, Controls, and Indicators	20
1.3.1 Front Panel	21
1.3.2 Front Panel Controls and Indicators	21
1.3.3 Rear Panel (X4500)	22
1.3.4 Rear Panel (X4540)	25
1.3.5 Component Locations (X4500)	27
1.3.6 Component Locations (X4540)	28
1.3.7 Sensor Information	29
1.4 Accessory Kit (X4500)	29
1.5 Accessory Kit (X4540)	30
1.6 Additional Options and Replaceable Components (X4500)	30
1.7 Additional Options and Replaceable Components (X4540)	32
Powering On and Configuring BIOS Settings	35
2.1 Powering On the Server	36
2.2 Powering Off the Server	37
2.3 Automatic Power-Off Events	37
2.4 Configuring BIOS Settings	38
2.4.1 Changing the Configuration of a BIOS Menu Item	38
2.5 Ethernet Port (NIC) Device and Driver Naming	39
2.5.1 NIC Naming Conventions	40
2.6 Power-On Self-Test (POST)	40
2.7 Load Optimal Default Settings During BIOS POST	40
2.8 BIOS Option ROM Size Limitation	41
2.8.1 AMD PowerNow! Feature Disabled by Default (Sun Fire X4500)	41
2.9 BIOS Setup Screens (X4500)	42
2.10 Device Boot Detection Priority (X4500)	44
2.11 Drives Mapping (X4500)	45
2.12 BIOS Setup Menu Screens (X4500)	46
2.12.1 BIOS Main Menu Screen (X4500)	47
2.12.2 BIOS Advanced Menu, Main Screen (X4500)	48
2.12.2.1 BIOS Advanced Menu, CPU Configuration Screen (X4500)	49
2.12.2.2 BIOS Advanced Menu, IDE Configuration Screen (X4500)	50
2.12.2.3 BIOS Advanced Menu, SuperIO Chipset Configuration Screen (X4500)	51
2.12.2.4 BIOS Advanced Menu, ACPI Configuration Screen (X4500)	52
2.12.2.5 BIOS Advanced Menu, Advanced ACPI Configuration Screen (X4500)	53
2.12.2.6 BIOS Advanced Menu, Event Logging Details Screen (X4500)	54
2.12.2.7 BIOS Advanced Menu, Hyper Transport Configuration Screen (X4500)	55
2.12.2.8 BIOS Advanced Menu, IPMI 2.0 Configuration Screen (X4500)	56
2.12.2.9 BIOS Advanced Menu, IPMI 2.0, View BMC Event Log Screen (X4500)	57
2.12.2.10 BIOS Advanced Menu, IPMI 2.0, LAN Configuration Screen (X4500)	58
2.12.2.11 BIOS Advanced Menu, IPMI 2.0, PEF Configuration Screen (X4500)	59
2.12.2.12 BIOS Advanced Menu, MPS Configuration Screen (X4500)	60
2.12.2.13 BIOS Advanced Menu, AMD PowerNow Configuration (X4500)	61
2.12.2.14 BIOS Advanced Menu, Remote Access Configuration Screen (X4500)	62
2.12.2.15 BIOS Advanced Menu, USB Configuration Screen (X4500)	63
2.12.3 BIOS PCI/PnP Menu (X4500)	64
2.12.4 BIOS Boot Menu, Main Screen (X4500)	65
2.12.4.1 BIOS Boot Menu, Boot Settings Configuration Screen (X4500)	66
2.12.4.2 BIOS Boot Menu, Boot Device Priority Screen (X4500)	67
2.12.4.3 BIOS Boot Menu, Disk Drives Screen (X4500)	68
2.12.4.4 BIOS Boot Menu, Removable Drives Screen (X4500)	69
2.12.4.5 BIOS Boot Menu, CD/DVD Drives Screen (X4500)	70
2.12.5 BIOS Security Settings Menu (X4500)	71
2.12.6 BIOS Chipset Menu, Main Screen (X4500)	72
2.12.6.1 BIOS Chipset Menu, NorthBridge Configuration Screen (X4500)	73
2.12.6.2 BIOS Chipset Menu, NorthBridge Memory Configuration Screen (X4500)	74
2.12.6.3 BIOS Chipset Menu, NorthBridge ECC Configuration Screen (X4500)	75
2.12.6.4 BIOS Chipset Menu, NorthBridge IOMMU Configuration Screen (X4500)	76
2.12.6.5 BIOS Chipset Menu, SouthBridge Configuration Screen (X4500)	77
2.12.7 BIOS Exit Options Menu Screen (X4500)	78
2.13 BIOS Setup Screens (X4540)	79
2.14 Device Boot Detection Priority (X4540)	81
2.15 Drives Mapping (X4540)	82
2.16 BIOS Setup Menu Screens (X4540)	84
2.16.1 BIOS Main Menu Screen (X4540)	85
2.16.2 BIOS Advanced Menu, Advanced Settings (X4540)	86
2.16.2.1 BIOS Advanced Menu, CPU Configuration (X4540)	87
2.16.2.2 BIOS Advanced Menu, IDE Configuration (X4540)	88
2.16.2.3 BIOS Advanced Menu, Hyper Transport Configuration (X4540)	89
2.16.2.4 BIOS Advanced Menu, ACPI Settings (X4540)	90
2.16.2.5 BIOS Advanced Settings, Advanced ACPI Settings (X4540)	90
2.16.2.6 BIOS Advanced Menu, Chipset ACPI Configuration (X4540)	91
2.16.2.7 BIOS Advanced Menu, General WHEA Configuration (X4540)	91
2.16.2.8 BIOS Advanced Menu, Event Logging Details (X4540)	92
2.16.2.9 BIOS Advanced Menu, IPMI 2.0 Configuration Screen (X4540)	93
2.16.2.10 BIOS Advanced Menu, LAN Configuration (X4540)	94
2.16.2.11 BIOS Advanced Menu, IPMI 2.0, LAN Configuration Screen (X4540)	95
2.16.2.12 BIOS Advanced Menu, MPS Configuration (X4540)	96
2.16.2.13 BIOS Advanced Menu, PCI Express Configuration (X4540)	97
2.16.2.14 BIOS Advanced Menu, Configure Remote Access (X4540)	98
2.16.2.15 BIOS Advanced Menu, USB Configuration (X4540)	99
2.16.3 BIOS PCI/PnP Menu (X4540)	100
2.16.4 BIOS Boot Settings Menu, Main Screen (X4540)	101
2.16.4.1 BIOS Boot Menu, Boot Settings Configuration Screen (X4540)	102
2.16.4.2 BIOS Boot Menu, Boot Device Priority Screen (X4540)	103
2.16.4.3 BIOS Boot Menu, Disk Drives Screen (X4540)	103
2.16.5 BIOS Security Settings Menu (X4540)	104
2.16.6 BIOS Advanced Chipset Settings, Main Screen (X4540)	105
2.16.6.1 BIOS Advanced Chipset Settings, NorthBridge Chipset Configuration (X4540)	106
2.16.6.2 BIOS Chipset Menu, NorthBridge Memory Configuration Setting (X4540)	107
2.16.6.3 BIOS Chipset Menu, ECC Configuration (X4540)	108
2.16.6.4 BIOS Chipset Menu, DRAM Timing Configuration (X4540)	109
2.16.6.5 BIOS Chipset Menu, SouthBridge Configuration Screen (X4540)	110
2.16.7 BIOS Exit Options Menu Screen (X4540)	111
2.17 Resetting the ILOM Root Password	112
2.18 Using the Clear CMOS Jumper	117
2.19 Resetting the SP	118
2.20 Updating BIOS	118
2.21 BIOS ROM Memory	119
2.22 Devices and PCI Slots	119
2.23 Disabling OPROM Scanning	120
Maintaining the Sun Fire X4500 and X4540 Servers	121
3.1 Tools and Supplies Needed	121
3.2 Locations of Components	122
3.3 FRUs/CRUs and BIOS Compatibility (X4540)	124
3.3.1 HyperTransport 3.0 Support	124
3.3.2 FRU/CRU Compatibility	125
3.3.3 Three-PSU 110V Option	125
3.4 System Model Numbers (X4540)	126
3.5 Disk Drive Compatibility	127
3.6 Servicetool FRU Update Procedure	128
3.7 Powering Off and Removing the Covers	130
3.7.1 Powering Off the Server	130
3.7.2 Removing the Server From the Rack	131
To Remove the Server From the Rack	132
To Remove the Drives Access Cover	133
To Install the Drives Access Cover	133
3.8 Finding the I/O Board and SP MAC Addresses	135
3.9 Replaceable Component Procedures	137
3.9.1 Cable Management Arm and Cable Management Bar	138
3.9.2 Slide Rail Documentation	138
3.9.3 Replacing the Power Distribution Board (FRU)	138
To Replace the Power Distribution Board	139
To Replace a Fan Module (CRU)	145
To Replace the Front Indicator Board (FRU)	148
To Replace a Hard Drive (CRU)	151
3.9.4 Replacing a Solid-State Drive (Sun Fire X4540 CRU)	155
3.9.4.1 SSD Restrictions	156
To Replace an SSD	156
3.9.5 Replacing a Power Supply (CRU)	160
To Access the Third Power Supply Bay	161
To Remove a Power Supply (CRU)	163
To Install a Power Supply	164
To Replace a Battery (CRU)	165
To Replace a CPU (FRU)	169
To Replace the GRASP Board (X4500) (FRU)	178
To Remove Memory Modules (DIMMs) (CRU)	181
To Install Memory Modules (DIMMs) (CRU)	184
To Install a PCI-X or PCIe Card (FRU)	185
To Install the System Enclosure (FRU)	187
3.9.6 Replacing the System Controller (FRU)	188
To Remove the System Controller (CRU)	190
To Install the System Controller (CRU)	193
System Specifications	197
BIOS POST Codes	199
B.1 Introduction to Power-On Self-Test (POST)	199
B.2 How to Load Optimal Default Settings During BIOS/POST	200
B.3 How BIOS POST Memory Testing Works	200
B.4 Redirecting Console Output	201
B.5 Changing POST Options	202
B.6 POST Codes	204
B.7 POST Code Checkpoints	206
Status Indicator LEDs	211
C.1 Front Panel LEDs	212
C.1.1 Rear Panel LEDs	214
C.2 Disk Drive and Fan Tray LEDs	216
C.2.1 CPU Board LEDs	220
C.3 GRASP Board LED (Sun Fire X4500)	223
C.4 CPU Module Debug LEDs	225
Connector Pinouts	227
D.1 USB Connector	227
D.2 Serial Connector	228
D.3 10/100BASE-T Connector	229
D.4 10/100/1000BASE-T Connector	230
D.5 VGA Video Connector	231
D.6 I/O-to-Disk Backplane Connectors	232
D.7 Power Supply Connector	239
D.8 Disk Backplane to Front Indicator Connector	240
D.9 Backplane To Disk Backplane Connector	241
D.10 Fan Tray Connectors	242
D.11 Fan Connectors	243
Power Reset and Initialization Sequences	245
E.1 Power-On Reset Sequence	245
E.2 Power-Off Sequence	248
I2E Bus Devices	251
F.1 Power-On Reset Sequence	251
F.2 I2E Bus Address Table	251
Early-Production Slide Rail and CMA Information	253
G.1 Removing the Cable Management Arm for the X4500	253
G.2 Removing the Cable Management Arm for the X4500	255
Device Paths	257
H.1 Sun Fire X4500 Device Paths	257
H.2 Sun Fire X4540 Device Paths	259

Match case Limit results 1 per page

B-6

Sun Fire X4500/X4540 Server Service Manual

•

May 2010

B.6

POST Codes

TABLE B-2

contains descriptions of each of the POST codes, listed in the same order in

which they are generated. These POST codes appear as a four-digit string that is a

combination of two-digit output from primary I/O port 80 and two-digit output from

secondary I/O port 81. In the POST codes listed in

TABLE B-2

, the first two digits are

from port 81 and the last two digits are from port 80.

TABLE B-2

POST Codes

Post Code

Description

00d0

Coming out of POR, PCI configuration space initialization, enabling 8111’s SMBus.

00d1

Keyboard controller BAT, waking up from PM, saving power-on CPUID in scratch CMOS.

00d2

Disable cache, full memory sizing, and verify that flat mode is enabled.

00d3

Memory detections and sizing in boot block, cache disabled, IO APIC enabled.

01d4

Test base 512 KB memory. Adjust policies and cache first 8MB.

01d5

Boot block code is copied from ROM to lower RAM. BIOS is now executing out of RAM.

01d6

Key sequence and OEM specific method is checked to determine if BIOS recovery is

forced. If next code is E0, BIOS recovery is being executed. Main BIOS checksum is tested.

01d7

Restoring CPUID; moving boot block-runtime interface module to RAM; determine

whether to execute serial flash.

01d8

Decompressing runtime module into RAM. Storing CPUID information in memory.

01d9

Copying main BIOS into memory.

01da

Giving control to BIOS POST.

0004

Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is

OK. If the CMOS checksum is bad, update CMOS with power-on default values.

00c2

Set up boot strap processor for POST. This includes frequency calculation, loading BSP

microcode, and applying user requested value for GART Error Reporting setup question.

00c3

Errata workarounds applied to the BSP (#78 & #110).

00c5

Enumerate and set up application processors. This includes microcode loading, and

workarounds for errata (#78, #110, #106, #107, #69, #63).

00c6

Reenable cache for boot strap processor, and apply workarounds in the BSP for errata

#106, #107, #69, and #63 if appropriate.

00c7

HT sets link frequencies and widths to their final values.

000a

Initializing the 8042 compatible Keyboard Controller.

000c

Detecting the presence of keyboard in KBC port.