Xerox 4540 Service Manual - Page 208

F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares

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TABLE B-3 POST Code Checkpoints (Continued) Post Code 75 78 7A 7C 84 85 87 8C 8D 8E 90 A0 A1 A2 A4 A7 A8 A9 AA AB AC Description Initialize Int-13 and prepare for IPL detection. Initializes IPL devices controlled by BIOS and option ROMs. Initializes remaining option ROMs. Generate and write contents of ESCD in NVRam. Log errors encountered during POST. Display errors to the user and receives the user responses. Execute BIOS setup if needed/requested. After all device initialization is done, programmed any user-selectable parameters relating to NB/SB, such as timing parameters, noncacheable regions and the shadow RAM cacheability, and do any other NB/SB/PCI-X/OEM-specific programming necessary during late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on setup questions. Get the DRAM scrub limits from each node. Workaround for erratum #101 is applied here. Build ACPI tables (if ACPI is supported). Program the peripheral parameters. Enable/Disable NMI as selected. Late POST initialization of system management interrupt. Check boot password if installed. Clean-up work required before booting to OS. Takes care of runtime image preparation for various BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if required. Initialize runtime language module. Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs. Prepare CPU for OS boot including final MTRR values. Wait for user input at config display if required. Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module. Prepare BBS for Int 19 boot. Any kind of chipset (NB/SB)-specific programming required during end-POST, just before giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming required during end-POST. Copy OEM-specific data from POST_DSEG to RUN_CSEG. B-10 Sun Fire X4500/X4540 Server Service Manual • May 2010

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B-10
Sun Fire X4500/X4540 Server Service Manual
•
May 2010
75
Initialize Int-13 and prepare for IPL detection.
78
Initializes IPL devices controlled by BIOS and option ROMs.
7A
Initializes remaining option ROMs.
7C
Generate and write contents of ESCD in NVRam.
84
Log errors encountered during POST.
85
Display errors to the user and receives the user responses.
87
Execute BIOS setup if needed/requested.
8C
After all device initialization is done, programmed any user-selectable parameters relating
to NB/SB, such as timing parameters, noncacheable regions and the shadow RAM
cacheability, and do any other NB/SB/PCI-X/OEM-specific programming necessary
during late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up
based on setup questions. Get the DRAM scrub limits from each node. Workaround for
erratum #101 is applied here.
8D
Build ACPI tables (if ACPI is supported).
8E
Program the peripheral parameters. Enable/Disable NMI as selected.
90
Late POST initialization of system management interrupt.
A0
Check boot password if installed.
A1
Clean-up work required before booting to OS.
A2
Takes care of runtime image preparation for various BIOS modules. Fill the free area in
F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the
runtime language module. Disables the system configuration display if required.
A4
Initialize runtime language module.
A7
Displays the system configuration screen if enabled. Initialize the CPUs before boot, which
includes the programming of the MTRRs.
A8
Prepare CPU for OS boot including final MTRR values.
A9
Wait for user input at config display if required.
AA
Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB
Prepare BBS for Int 19 boot.
AC
Any kind of chipset (NB/SB)-specific programming required during end-POST, just before
giving control to runtime code booting to OS. Programmed the system BIOS (0F0000h
shadow RAM) cacheability. Ported to handle any OEM specific programming required
during end-POST. Copy OEM-specific data from POST_DSEG to RUN_CSEG.
TABLE B-3
POST Code Checkpoints
(Continued)
Post Code
Description