Xerox 4540 Service Manual - Page 206

B.7 POST Code Checkpoints

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B.7 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. TABLE B-3 describes the checkpoints that might occur during the POST portion of the BIOS. These two-digit checkpoints are the output from primary I/O port 80. TABLE B-3 POST Code Checkpoints Post Code 03 04 05 06 C0 C1 C2 C3 C5 C6 C7 0A 0B 0C Description Disable NMI, Parity, video for EGA, and DMA controllers. At this point, POST code is still executing out of BIOS ROM. Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system. Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. Do R/W test to CH-2 count register. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to POSTINT1ChHandlerBlock. Early CPU Init Start-Disable Cache-Init Local APIC. Set up boot strap processor information. Set up boot strap processor for POST. This includes calculating the frequency, loading BSP microcode, and applying user-requested value for GART Error Reporting setup question. Errata workarounds applied to the BSP (#78 & #110). Enumerate and set up application processors. This includes microcode loading, and workarounds for errata (#78, #110, #106, #107, #69, #63). Reenable cache for boot strap processor, and apply workarounds in the BSP for errata #106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs are left in the CLI HLT state. The HT sets link frequencies and widths to their final values. This routine gets called after CPU frequency has been calculated to prevent bad programming. Initializes the 8042 compatible keyboard controller. Detects the presence of PS/2 mouse. Detects the presence of keyboard in KBC port. B-8 Sun Fire X4500/X4540 Server Service Manual • May 2010

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B-8
Sun Fire X4500/X4540 Server Service Manual
•
May 2010
B.7
POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS
pre-boot process.
TABLE B-3
describes the checkpoints that might occur during the
POST portion of the BIOS. These two-digit checkpoints are the output from primary
I/O port 80.
TABLE B-3
POST Code Checkpoints
Post Code
Description
03
Disable NMI, Parity, video for EGA, and DMA controllers. At this point, POST code is still
executing out of BIOS ROM.
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is
bad, update CMOS with power-on default values and clear passwords. Initialize status
register A. Initializes data variables that are based on CMOS setup questions. Initializes
both the 8259 compatible PICs in the system.
05
Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06
Do R/W test to CH-2 count register. Initialize CH-0 as system timer. Install the
POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch
vector to POSTINT1ChHandlerBlock.
C0
Early CPU Init Start-Disable Cache-Init Local APIC.
C1
Set up boot strap processor information.
C2
Set up boot strap processor for POST. This includes calculating the frequency, loading BSP
microcode, and applying user-requested value for GART Error Reporting setup question.
C3
Errata workarounds applied to the BSP (#78 & #110).
C5
Enumerate and set up application processors. This includes microcode loading, and
workarounds for errata (#78, #110, #106, #107, #69, #63).
C6
Reenable cache for boot strap processor, and apply workarounds in the BSP for errata
#106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought
and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs
are left in the CLI HLT state.
C7
The HT sets link frequencies and widths to their final values. This routine gets called after
CPU frequency has been calculated to prevent bad programming.
0A
Initializes the 8042 compatible keyboard controller.
0B
Detects the presence of PS/2 mouse.
0C
Detects the presence of keyboard in KBC port.