Intel SL8K2 Specification Update - Page 10

Summary Tables of Changes R NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA The Processor Signals Page-Fault R10 X X X X X X X X X No Fix Exception (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction R11 X X X X X X X X X No Fix FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions R12 X X X X X X X X X No Fix Processor Issues Inconsistent Transaction Size Attributes for Locked Operation When the Processor Is in the R13 X X X X X X X X X No System Management Mode (SMM), Fix Debug Registers May Be Fully Writeable Shutdown and IERR# May Result R14 X X X X X X X X X No Due to a Machine Check Exception Fix on a Hyper-Threading Technology Enabled Processor R15 X X X X X X X X X No Fix Processor May Hang under Certain Frequencies and 12.5% STPCLK# Duty Cycle System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL) R16 X X X X X X X X X No Transaction to Occur to the Same Fix Cache Line Address as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL} R17 X X X X X X X X X No Fix A Write to an APIC Registers Sometimes May Appear to Have Not Occurred R18 X Fixed Some Front Side Bus I/O Specifications are not Met R19 X X X X X X X X X No Parity Error in the L1 Cache May Fix Cause the Processor to Hang R20 X Fixed BPM4# Signal Not Being Asserted According to Specification R21 X X X X X Fixed Sequence of Locked Operations Can Cause Two Threads to Receive Stale Data and Cause Application Hang R22 X X X Fixed A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to be Reported to the #GP Exception Handler R23 X X X X X X X X X No Fix Bus Locks and SMC Detection May Cause the Processor to Hang Temporarily 10 Intel® Pentium® 4 Processor on 90 nm Process Specification Update