Intel SL8K2 Specification Update - Page 70

Errata R R117. VMExit after MOV SS and a Waiting x87 Instruction May not Clear the Interruptibility State in the VMM's Working VMCS Problem: When Guest software executes a waiting x87 instruction, after an interrupt window which was closed due to blocking by MOVSS, a VM exit may occur due to Interrupt Window exiting = 1 in the Processor-Based VM-Execution Controls of the Controlling VMCS. This causes blocking by MOVSS bit in Interruptibility State to be incorrectly set in the VMM's Working VMCS. Implication: If a VM Exit occurs due to the Guest Software executing a waiting x87 instruction after a MOVSS and the VMM injects a hardware interrupt or an NMI to the Guest without explicitly clearing the Blocking by MOVSS bit in the Interruptibility State field in the working VMCS, then, the VMM will see a spurious VM Entry failure. Workaround: The VM Monitor should explicitly clear the Blocking by MOVSS bit in the Interruptibility State field in the working VMCS, before injecting a hardware interrupt or an NMI to the Guest software. Status: For the steppings affected, see the Summary Tables of Changes. R118. VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field Problem: Processors supporting Intel® Virtualization Technology can execute VMCALL from within the Virtual Machine Monitor (VMM) to activate dual-monitor treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to values inconsistent with VMX Capability MSRs, VMCALL may not VMFail. Implication: VMCALL executed to activate dual-monitor treatment of SMIs and SMM may not VMFail due to incorrect reserved bit settings in VM-Exit control field. Workaround: Software should ensure that all VMCS reserved bits are set to values consistent with VMX Capability MSRs. Status: For the steppings affected, see the Summary Tables of Changes. 70 Intel® Pentium® 4 Processor on 90 nm Process Specification Update