Intel SL8K2 Specification Update - Page 55

Errata R R73. MCA Corrected Memory Hierarchy Error Counter May Not Increment Correctly Problem: An MCA corrected memory hierarchy error counter can report a maximum of 255 errors. Due to the incorrect increment of the counter, the number of errors reported may be incorrect. Implication: Due to this erratum, the MCA counter may report incorrect number of soft errors. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. R74. BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer Problem: If the BTS/PEBS buffer is defined such that: • The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is not an integer multiple of the corresponding record sizes • BTS/PEBS absolute maximum is less than a record size from the end of the virtual address space • The record that would cross BTS/PEBS absolute maximum will also continue past the end of the virtual address space A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64 boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer. Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (Intel EM64T mode), and defines the buffer such that it does not hold an integer multiple of records can update memory outside the BTS/PEBS buffer. Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is integer multiple of the corresponding record sizes as recommended in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3. Status: For the steppings affected, see the Summary Tables of Changes. R75. The Base of an LDT (Local Descriptor Table) Register May be Non-zero on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be nonzero. Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector. There may be no #GP fault in response to this access. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 55