Intel SL8K2 Specification Update - Page 18

Summary Tables of Changes R NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA R111 X No Fix FS/GS Base MSRs can be Loaded from MSR-Load Areas during VM Entry or VM Exit R112 X Plan Fix NMI-blocking Information Recorded in VMCS May be Incorrect after a #GP on an IRET Instruction R113 VMLAUNCH/VMRESUME May Not X Plan Fail when VMCS is Programmed to Fix Cause VM Exit to Return to a Different Mode R114 X Fixed Upper 32 bits of 'From' Address Reported through LBR or LER MSRs, BTMs or BTSs May be Incorrect R115 X Plan Fix VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with Hyper-Threading Enabled L2 Cache ECC Machine Check R116 X X X X X X X X X No Errors May be erroneously Reported Fix after an Asynchronous RESET# Assertion R117 VMExit after MOV SS and a Waiting X Plan x87 Instruction May not Clear the Fix Interruptibility State in the VMM's Working VMCS R118 VMCALL to Activate Dual-monitor X Plan Treatment of SMIs and SMM Fix Ignores Reserved Bit settings in VM-exit Control Field R119 X X X X X X X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that R120 X X X X X X X X X No Crosses a Cache Line without Fix Proper Semaphores or Barriers May Expose a Memory Ordering Issue The IA32_MC0_STATUS and R121 X X X X X X X X X No Fix IA32_MC1_STATUS Overflow Bit is not set when Multiple Uncorrectable Machine Check Errors Occur at the Same Time R122 X X X X X X X X X No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags May be set Incorrectly A Continuous Loop Executing Bus R123 X X X X X X X X X No Fix Lock Transactions on One Logical Processor may Prevent Another Logical Processor from Acquiring Resources NOTES: 1. Only applies to Pentium® 4 processor on 90 nm Process in the 478-pin package 2. Prefix "L" denotes Pentium 4 processor on 90 nm Process in the 775-land LGA package 18 Intel® Pentium® 4 Processor on 90 nm Process Specification Update