Intel SL8K2 Specification Update - Page 61

Incorrectly in the Branch Trace Store BTS Memory Record or in

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Errata R R91. A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly in the Branch Trace Store (BTS) Memory Record or in the Precise Event Based Sampling (PEBS) Memory Record Problem: On a processor supporting Intel® EM64T, • If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0). • If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh, the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0). Implication: Intel has not observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R92. It is Possible That Two specific Invalid Opcodes May Cause Unexpected Memory Accesses Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor may respond instead, with a load to an incorrect address. Implication: This erratum may cause unpredictable system behavior or system hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R93. At Core-to-bus Ratios of 16:1 and Above Defer Reply Transactions with Non-zero REQb Values May Cause a Front Side Bus Stall Problem: Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are met: 1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b, and 2. The operating bus ratio is 16:1 or higher. When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall for the Defer Reply transaction. Such an event will block further progress on the FSB. Implication: If this erratum occurs, the system may hang. Intel chipsets avoid the REQb conditions required to observe this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 61

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
61
R91.
A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported
Incorrectly in the Branch Trace Store (BTS) Memory Record or in the
Precise Event Based Sampling (PEBS) Memory Record
Problem:
On a processor supporting Intel
®
EM64T,
•
If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value
of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh
when they should be 0).
•
If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh,
the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to
FFFFFFFFh when they should be 0).
Implication:
Intel has not observed this erratum on any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R92.
It is Possible That Two specific Invalid Opcodes May Cause Unexpected
Memory Accesses
Problem:
A processor is expected to respond with an undefined opcode (#UD) fault when executing either
opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the
processor may respond instead, with a load to an incorrect address.
Implication:
This erratum may cause unpredictable system behavior or system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R93.
At Core-to-bus Ratios of 16:1 and Above Defer Reply Transactions with
Non-zero REQb Values May Cause a Front Side Bus Stall
Problem:
Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are
met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b,
and
2. The operating bus ratio is 16:1 or higher.
When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall
for the Defer Reply transaction.
Such an event will block further progress on the FSB.
Implication:
If this erratum occurs, the system may hang.
Intel chipsets avoid the REQb conditions required to
observe this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.