Intel SL8K2 Specification Update - Page 52

When the Execute Disable Bit Function Is Enabled a fault in

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Errata R R62. Enhanced Halt State (C1E) Voltage Transition May Affect a System's Power Management in a Hyper-Threading Technology Enabled Processor Problem: In an Hyper-Threading Technology enabled system, the second logical Processor may fail to wake up from "Wait-for-SIPI" state during a C1E voltage transition. Implication: This erratum may affect a system's entry into the power management mode offered by the C1E event for HT Technology enabled platforms. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R63. Enhanced Halt State (C1E) May Not Be Entered in a Hyper-Threading Technology Enabled Processor Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on an HT Technology enabled system, the processor will not enter C1E until the next SIPI wakeup event for the second logical processor. Implication: Due to this erratum, the processor will not enter C1E state. Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to issuing the first SIPI to the second logical processor. Status: For the steppings affected, see the Summary Tables of Changes. R64. When the Execute Disable Bit Function Is Enabled a Page-fault in a Mispredicted Branch May Result in a Page-fault Exception Problem: If a page-fault in a mispredicted branch occurs in the ITLB, it should not be reported by the processor. However, if the execute disable bit function is enabled (IA32_EFER.NXE = 1) and there is a page-fault in a mispredicted branch in the ITLB, a page-fault exception may occur. Implication: When this erratum occurs, a page-fault exception may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R65. Execute Disable Bit Set with AD Assist May Cause Livelock Problem: If Execute Disable Bit is set and the resulting page requires the processor to set the A and/or D bit (Access and/or Dirty bit) in the PTE, then the processor may livelock. Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating system failure. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 52 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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Errata
R
52
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R62.
Enhanced Halt State (C1E) Voltage Transition May Affect a System’s Power
Management in a Hyper-Threading Technology Enabled Processor
Problem:
In an Hyper-Threading Technology enabled system, the second logical Processor may fail to
wake up from "Wait-for-SIPI" state during a C1E voltage transition.
Implication:
This erratum may affect a system’s entry into the power management mode offered by the C1E
event for HT Technology enabled platforms.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R63.
Enhanced Halt State (C1E) May Not Be Entered in a Hyper-Threading
Technology Enabled Processor
Problem:
If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on
an HT Technology enabled system, the processor will not enter C1E until the next SIPI wakeup
event for the second logical processor.
Implication:
Due to this erratum, the processor will not enter C1E state.
Workaround:
If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to
issuing the first SIPI to the second logical processor.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R64.
When the Execute Disable Bit Function Is Enabled a Page-fault in a
Mispredicted Branch May Result in a Page-fault Exception
Problem:
If a page-fault in a mispredicted branch occurs in the ITLB, it should not be reported by the
processor. However, if the execute disable bit function is enabled (IA32_EFER.NXE = 1) and
there is a page-fault in a mispredicted branch in the ITLB, a page-fault exception may occur.
Implication:
When this erratum occurs, a page-fault exception may occur.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R65.
Execute Disable Bit Set with AD Assist May Cause Livelock
Problem:
If Execute Disable Bit is set and the resulting page requires the processor to set the A and/or D bit
(Access and/or Dirty bit) in the PTE, then the processor may livelock.
Implication:
When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.