Intel SL8K2 Specification Update - Page 43

Missing Stop Grant Acknowledge Special Bus Cycle May Cause a System

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Errata R R32. STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang Problem: The assertion of STPCLK# signal before a logical processor awakens from the "Wait-forSIPI" state for the first time, may cause a system hang. A processor supporting Hyper-Threading Technology may fail to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in response to the second STPCLK# assertion Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang. Workaround: BIOS should initialize the second thread of the processor supporting Hyper-Threading Technology prior to STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R33. Missing Stop Grant Acknowledge Special Bus Cycle May Cause a System Hang Problem: A Stop Grant Acknowledge special bus cycle being deferred by the processor for a period of time long enough for the chipset to de-assert and then re-assert STPCLK# signal may cause a system hang. A processor supporting Hyper-Threading Technology may fail to detect the de-assertion and re-assertion of STPCLK# signal, and may not issue a Stop Grant Acknowledge special bus cycle in response to the second STPCLK# assertion. Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R34. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register. Due to this erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access (to the PDE portion of the page table) that may be directed to an incorrect memory address. Implication: The results of the access to the PDE will not be consumed by the processor so the return of incorrect data is benign. However, the system may hang if the access to the PDE does not complete with data (e.g. infinite number of retries). Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 43

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
43
R32.
STPCLK# Signal Assertion under Certain Conditions May Cause a
System Hang
Problem:
The assertion of STPCLK# signal before a logical processor awakens from the "Wait-for-
SIPI" state for the first time, may cause a system hang. A processor supporting Hyper-Threading
Technology may fail to initialize appropriately, and may not issue a Stop Grant Acknowledge
special bus cycle in response to the second STPCLK# assertion
Implication:
When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround:
BIOS should initialize the second thread of the processor supporting Hyper-Threading
Technology prior to STPCLK# assertion. Additionally, it is possible for the BIOS to contain a
workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R33.
Missing Stop Grant Acknowledge Special Bus Cycle May Cause a System
Hang
Problem:
A Stop Grant Acknowledge special bus cycle being deferred by the processor for a period of time
long enough for the chipset to de-assert and then re-assert STPCLK# signal may cause a system
hang. A processor supporting Hyper-Threading Technology may fail to detect the de-assertion
and re-assertion of STPCLK# signal, and may not issue a Stop Grant Acknowledge special bus
cycle in response to the second STPCLK# assertion.
Implication:
When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R34.
Changes to CR3 Register Do Not Fence Pending Instruction Page Walks
Problem:
When software writes to the CR3 register, it is expected that all previous/outstanding code, data
accesses and page walks are completed using the previous value in CR3 register. Due to this
erratum, it is possible that a pending instruction page walk is still in progress, resulting in an
access (to the PDE portion of the page table) that may be directed to an incorrect memory
address.
Implication:
The results of the access to the PDE will not be consumed by the processor so the return of
incorrect data is benign. However, the system may hang if the access to the PDE does not
complete with data (e.g. infinite number of retries).
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.