Intel SL8K2 Specification Update - Page 54

Resume Flag Bit May Be Delayed by an RFO Request for Ownership

Get Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU PDF manuals and user guides
UPC - 683728107215
View all Intel SL8K2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 54 highlights

Errata R R70. The IA32_MCi_STATUS MSR May Improperly Indicate that Additional MCA Information May Have Been Captured Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured. Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and IA32_MCi_MISC may not correspond to the reported machine-check error, even though the ADDRV and MISCV are asserted. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R71. Execution of an Instruction with a Code Breakpoint Inhibited by the RF (Resume Flag) Bit May Be Delayed by an RFO (Request for Ownership) from Another Bus Agent Problem: In Hyper-Threading Technology enabled parts, execution of an instruction with a code breakpoint inhibited by the RF bit may be delayed by an RFO from another bus agent. An infinite stream of these RFOs may prevent the software from making forward progress. Implication: If this erratum occurs, the software may experience a delay in making forward progress or it may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R72. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes. Implication: A Single Step trap will be taken when not expected. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 54 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
Errata
R
54
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R70.
The IA32_MCi_STATUS MSR May Improperly Indicate that Additional MCA
Information May Have Been Captured
Problem:
When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of
the IA32_MCi_STATUS register may be asserted even though the contents of the
IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Implication:
If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and
IA32_MCi_MISC may not correspond to the reported machine-check error, even though the
ADDRV and MISCV are asserted.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R71.
Execution of an Instruction with a Code Breakpoint Inhibited by the RF
(Resume Flag) Bit May Be Delayed by an RFO (Request for Ownership)
from Another Bus Agent
Problem:
In Hyper-Threading Technology enabled parts, execution of an instruction with a code breakpoint
inhibited by the RF bit may be delayed by an RFO from another bus agent.
An infinite stream of
these RFOs may prevent the software from making forward progress.
Implication:
If this erratum occurs, the software may experience a delay in making forward progress or it
may hang. Intel has not observed this erratum with any commercially available software or
system.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R72.
With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked
FP Exception May Take Single Step Trap before Retirement of Instruction
Problem:
If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for
external events to occur, including a transition to a lower power state.
When resuming from the
lower power state, it may be possible to take the single step trap before the execution of the
original FP instruction completes.
Implication:
A Single Step trap will be taken when not expected.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.