Intel SL8K2 Specification Update - Page 15

Summary Tables of Changes R NO. C01 D0 LD02 E0 LE02 G11 LG12 LN02 LR02 Plan ERRATA Memory Ordering Failure May Occur with Snoop Filtering Third R77 X X X X X X X X X No Party Agents after Issuing and Fix Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus Locked Write) Transaction Control Register 2 (CR2) Can be R78 X X X X X X X X X No Updated during a REP Fix MOVS/STOS Instruction with Fast Strings Enabled TPR (Task Priority Register) R79 X X X X Fixed Updates during Voltage Transitions of Power Management Events May Cause a System Hang R80 X X X X X No Fix REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System Hang An REP MOVS or an REP STOS Instruction with RCX >= 2^32 May Fail to Execute to Completion or R81 X X X X Fixed May Write to Incorrect Memory Locations on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) An REP LODSB or an REP LODSD or an REP LODSQ Instruction with R82 X X X X Fixed RCX >= 2^32 May Cause a System Hang on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) A Data Access which Spans Both R83 X X X X No the Canonical and the NonFix Canonical Address Space May Hang the System R84 X X X X X X X X Fixed Running in SMM (System Management Mode) And L1 Data Cache Adaptive Mode May Cause Unexpected System Behavior when SMRAM is Mapped to Cacheable Memory R85 X CPUID Instruction Incorrectly Fixed Reports CMPXCH16B as Supported Unaligned PDPTR (Page-Directory- R86 X X X X X Fixed Pointer) Base with 32-bit Mode PAE (Page Address Extension) Paging May Cause Processor to Hang Intel® Pentium® 4 Processor on 90 nm Process Specification Update 15