Intel SL8K2 Specification Update - Page 62

Front Side Bus Machine Checks May be Reported as a Result of On-Going

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Errata R R94. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after RESET# is Asserted Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may issue transactions up to 6 FSB clocks after the RESET# is asserted Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R95. Front Side Bus Machine Checks May be Reported as a Result of On-Going Transactions during Warm Reset Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to occur during RESET# assertions. Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not block new transactions during RESET# assertions. Status: For the steppings affected, see the Summary Tables of Changes R96. CPUID Feature Flag Reports LAHF/SAHF as Unavailable however the Execution of LAHF/SAHF May Not Result in an Invalid Opcode Exception Problem: As described in the IA-32 Intel® Architecture Software Developer's Manual, support for LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors. The CPUID feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode, even though the instructions are supported and able to be executed without an Invalid Opcode exception. Implication: The CPUID Feature Flag incorrectly reports LAHF/SAHF instructions as unavailable in 64-bit mode; however they can be executed normally. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 62 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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Errata
R
62
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R94.
The Processor May Issue Front Side Bus Transactions up to 6 Clocks after
RESET# is Asserted
Problem:
The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and
up to 6 FSB clocks after RESET# is asserted in the case of a warm reset.
A warm reset is where
the chipset asserts RESET# when the system is running.
Implication:
The processor may issue transactions up to 6 FSB clocks after the RESET# is asserted
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R95.
Front Side Bus Machine Checks May be Reported as a Result of On-Going
Transactions during Warm Reset
Problem:
Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the
transactions are initiated or in-progress during a warm reset.
A warm reset is where the chipset
asserts RESET# when the system is running.
Implication:
The processor may log FSB protocol/signal integrity machine checks if transactions are allowed
to occur during RESET# assertions.
Workaround:
BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not
block new transactions during RESET# assertions.
Status:
For the steppings affected, see the
Summary Tables of Changes
R96.
CPUID Feature Flag Reports LAHF/SAHF as Unavailable however the
Execution of LAHF/SAHF May Not Result in an Invalid Opcode Exception
Problem:
As described in the IA-32 Intel
®
Architecture Software Developer’s Manual, support for
LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors. The CPUID
feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode, even
though the instructions are supported and able to be executed without an Invalid Opcode
exception.
Implication:
The CPUID Feature Flag incorrectly reports LAHF/SAHF instructions as unavailable in 64-bit
mode; however they can be executed normally.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.