Intel SL8K2 Specification Update - Page 38

Errata R R17. A Write to an APIC Registers Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not lost. Implication: In this example the processor may allow interrupts to be accepted but may delay their service. Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register write. This will force the store to the APIC register before any subsequent instructions are executed. No commercial operating system is known to be impacted by this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R18. Some Front Side Bus I/O Specifications Are Not Met Problem: The following front side bus I/O specifications are not met: • The VIH(min) for the GTL+ signals is specified as GTLREF + (0.10 * VCC) [V]. • The VIH(min) for the Asynchronous GTL+ signals is specified as Vcc/2 + (0.10 * VCC) [V]. Implication: This erratum can cause functional failures depending upon system bus activity. It can manifest itself as data parity, address parity, and/or machine check errors. Workaround: Due to this erratum, the system should meet the following voltage levels and processor timings: • The VIH(min) for GTL+ signals is now GTLREF + (0.20 * VCC) [V]. • The VIH(min) for the Asynchronous GTL+ signals is now Vcc/2 + (0.20 * VCC) [V]. Status: For the steppings affected, see the Summary Tables of Changes. R19. Parity Error in the L1 Cache May Cause the Processor to Hang Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the processor may hang while trying to evict the line. Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 38 Intel® Pentium® 4 Processor on 90 nm Process Specification Update