Intel SL8K2 Specification Update - Page 35

EMON Event Counting of x87 Loads May Not Work As Expected

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Errata R R8. EMON Event Counting of x87 Loads May Not Work As Expected Problem: If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the FPU Operand Data Pointer (FDP) may become corrupted. Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked. If floating point exceptions are unmasked, then performance counting of x87 loads should be disabled. Status: For the steppings affected, see the Summary Tables of Changes. R9. System Bus Interrupt Messages without Data Which Receive a HardFailure Response May Hang the Processor Problem: When a system bus agent (processor or chipset) issues an interrupt transaction without data onto the system bus and the transaction receives a HardFailure response, a potential processor hang can occur. The processor, which generates an inter-processor interrupt (IPI) that receives the HardFailure response, will still log the MCA error event cause as HardFailure, even if the APIC causes a hang. Other processors, which are true targets of the IPI, will also hang on hardfailwithout-data, but will not record an MCA HardFailure event as the cause. If a HardFailure response occurs on a system bus interrupt message with data, the APIC will complete the operation so as not to hang the processor. Implication: The processor may hang. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R10. The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction Problem: If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an unlocked CMPXCHG8B instruction, then #PF will be flagged. Implication: Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception (#PF) will be affected since #PF is signaled in this case. Workaround: Remove the software's dependency on #AC having precedence over #PF. Alternately, correct the page fault in the page fault handler and then restart the faulting instruction Status: For the stepping affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 35

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
35
R8.
EMON Event Counting of x87 Loads May Not Work As Expected
Problem:
If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the
FPU Operand Data Pointer (FDP) may become corrupted.
Implication:
When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted.
Workaround:
This erratum will not occur with floating point exceptions masked. If floating point exceptions are
unmasked, then performance counting of x87 loads should be disabled.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R9.
System Bus Interrupt Messages without Data Which Receive a HardFailure
Response May Hang the Processor
Problem:
When a system bus agent (processor or chipset) issues an interrupt transaction without data onto
the system bus and the transaction receives a HardFailure response, a potential processor hang
can occur. The processor, which generates an inter-processor interrupt (IPI) that receives the
HardFailure response, will still log the MCA error event cause as HardFailure, even if the APIC
causes a hang. Other processors, which are true targets of the IPI, will also hang on hardfail-
without-data, but will not record an MCA HardFailure event as the cause. If a HardFailure
response occurs on a system bus interrupt message with data, the APIC will complete the
operation so as not to hang the processor.
Implication:
The processor may hang.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R10.
The Processor Signals Page-Fault Exception (#PF) Instead of Alignment
Check Exception (#AC) on an Unlocked CMPXCHG8B Instruction
Problem:
If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an
unlocked CMPXCHG8B instruction, then #PF will be flagged.
Implication:
Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception
(#PF) will be affected since #PF is signaled in this case.
Workaround:
Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the
page fault in the page fault handler and then restart the faulting instruction
Status:
For the stepping affected, see the
Summary Tables of Changes.