Intel SL8K2 Specification Update - Page 59

Mode May Cause Unexpected System Behavior when SMRAM is Mapped

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Errata R R84. Running in SMM (System Management Mode) And L1 Data Cache Adaptive Mode May Cause Unexpected System Behavior when SMRAM is Mapped to Cacheable Memory Problem: In a Hyper-Threading Technology-enabled system, unexpected system behavior may occur if a change is made to the value of the CR3 result from an RSM (Resume From System Management) instruction while in L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit. Implication: This erratum can have multiple failure symptoms including incorrect data in memory. Intel has not observed this erratum with any commercially available software. Workaround: Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode control (bit 24) of the IA32_MISC_ENABLES MSR (0x1a0) to 1. Status: For the steppings affected, see the Summary Tables of Changes. R85. CPUID instruction incorrectly reports CMPXCH16B as supported Problem: A read of the CMPXCHG16B feature flag improperly indicates that the CMPXCHG16B instruction is supported. Implication: When a processor supporting Intel EM64T attempts to execute a CMPXCH16B instruction, the system may hang rather than #UD fault. Workaround: It is possible for the BIOS to contain a workaround for this erratum, such that the CMPXCH16B feature flag indicates that the instruction is not supported, and the execution of the CMPXCHG16B instruction results in a #UD fault. Status: For the steppings affected, see the Summary Tables of Changes. R86. Unaligned PDPTR (Page-Directory-Pointer) Base with 32-bit Mode PAE (Page Address Extension) Paging May Cause Processor to Hang Problem: When the MOV to CR0, CR3 or CR4 instructions are executed in legacy PAE paging mode and software is using an unaligned PDPTR base the processor may hang or an incorrect page translation may be used. Implication: Software that is written according to Intel's alignment specification (32-byte aligned PDPTR Base) will not encounter this erratum. Intel has not observed this erratum with commercially available software. Systems may hang or experience unpredictable behavior when this erratum occurs. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 59

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
59
R84.
Running in SMM (System Management Mode) And L1 Data Cache Adaptive
Mode May Cause Unexpected System Behavior when SMRAM is Mapped to
Cacheable Memory
Problem:
In a Hyper-Threading Technology-enabled system, unexpected system behavior may occur if a
change is made to the value of the CR3 result from an RSM (Resume From System Management)
instruction while in L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24).
This behavior will only be visible when SMRAM is mapped into WB/WT cacheable memory on
SMM entry and exit.
Implication:
This erratum can have multiple failure symptoms including incorrect data in memory.
Intel has
not observed this erratum with any commercially available software.
Workaround:
Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode control (bit 24)
of the IA32_MISC_ENABLES MSR (0x1a0) to 1.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R85.
CPUID instruction incorrectly reports CMPXCH16B as supported
Problem:
A read of the CMPXCHG16B feature flag improperly indicates that the CMPXCHG16B
instruction is supported.
Implication:
When a processor supporting Intel EM64T attempts to execute a CMPXCH16B instruction, the
system may hang rather than #UD fault.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum, such that the CMPXCH16B
feature flag indicates that the instruction is not supported, and the execution of the
CMPXCHG16B instruction results in a #UD fault.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R86.
Unaligned PDPTR (Page-Directory-Pointer) Base with 32-bit Mode PAE
(Page Address Extension) Paging May Cause Processor to Hang
Problem:
When the MOV to CR0, CR3 or CR4 instructions are executed in legacy PAE paging mode and
software is using an unaligned PDPTR base the processor may hang or an incorrect page
translation may be used.
Implication:
Software that is written according to Intel’s alignment specification (32-byte aligned PDPTR
Base) will not encounter this erratum. Intel has not observed this erratum with commercially
available software. Systems may hang or experience unpredictable behavior when this erratum
occurs.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes
.