Intel SL8K2 Specification Update - Page 42

Memory Aliasing of s As Uncacheable Memory Type and Write Back

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Errata R R29. Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation Is Enabled in a Processor Supporting Hyper-Threading Technology Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock Modulation on both logical processors, the processor is expected to select the lowest duty cycle of the two potentially different values. When one logical processor enters the AUTOHALT state, the duty cycle implemented should be unaffected by the halted logical processor. Due to this erratum, the duty cycle is incorrectly chosen to be the higher duty cycle of both logical processors. Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock Modulation is enabled on both logical processors. Workaround: None identified at this time Status: For the stepping affected, see the Summary Tables of Changes. R30. Memory Aliasing of Pages As Uncacheable Memory Type and Write Back (WB) May Hang the System Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO) retries. Implication: This erratum has not been observed in any commercially available operating system or application. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang. Workaround: The pages should not be mapped as either UC or WC and WB at the same time. Status: For the stepping affected, see the Summary Tables of Changes. R31. Interactions between the Instruction Translation Lookaside Buffer (ITLB) and the Instruction Streaming Buffer May Cause Unpredictable Software Behavior Problem: Complex interactions within the instruction fetch/decode unit may make it possible for the processor to execute instructions from an internal streaming buffer containing stale or incorrect information. Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in unpredictable software behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the stepping affected, see the Summary Tables of Changes. 42 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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Errata
R
42
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R29.
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation Is
Enabled in a Processor Supporting Hyper-Threading Technology
Problem:
When a processor supporting Hyper-Threading Technology enables On-Demand Clock
Modulation on both logical processors, the processor is expected to select the lowest duty cycle of
the two potentially different values. When one logical processor enters the AUTOHALT state, the
duty cycle implemented should be unaffected by the halted logical processor. Due to this erratum,
the duty cycle is incorrectly chosen to be the higher duty cycle of both logical processors.
Implication:
Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock Modulation is
enabled on both logical processors.
Workaround:
None identified at this time
Status:
For the stepping affected, see the
Summary Tables of Changes.
R30.
Memory Aliasing of Pages As Uncacheable Memory Type and Write Back
(WB) May Hang the System
Problem:
When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB,
under certain bus and memory timing conditions, the system may loop in a continual sequence of
UC fetch, implicit writeback, and Request For Ownership (RFO) retries.
Implication:
This erratum has not been observed in any commercially available operating system or
application. The aliasing of memory regions, a condition necessary for this erratum to occur, is
documented as being unsupported in the
IA-32
Intel
®
Architecture Software Developer's Manual
,
Volume 3
,
section 10.12.4, Programming the PAT. However, if this erratum occurs the system
may hang.
Workaround:
The pages should not be mapped as either UC or WC and WB at the same time.
Status:
For the stepping affected, see the
Summary Tables of Changes.
R31.
Interactions between the Instruction Translation Lookaside Buffer (ITLB)
and the Instruction Streaming Buffer May Cause Unpredictable Software
Behavior
Problem:
Complex interactions within the instruction fetch/decode unit may make it possible for the
processor to execute instructions from an internal streaming buffer containing stale or incorrect
information.
Implication:
When this erratum occurs, an incorrect instruction stream may be executed resulting in
unpredictable software behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the stepping affected, see the
Summary Tables of Changes.