Intel SL8K2 Specification Update - Page 45

Data Breakpoints on the High Half of a Floating Point Line Split May Not

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Errata R R37. Using STPCLK# and Executing Code from Very Slow Memory Could Lead to a System Hang Problem: The system may hang when the following conditions are met: 1. Periodic STPCLK# mechanism is enabled via the chipset 2. Hyper-Threading Technology is enabled 3. One logical processor is waiting for an event (i.e. hardware interrupt) 4. The other logical processor executes code from very slow memory such that every code fetch is deferred long enough for the STPCLK# to be re-asserted. Implication: If this erratum occurs, the processor will go into and out of the sleep state without making forward progress, since the logical processor will not be able to service any pending event. This erratum has not been observed in any commercial platform running commercial software. Workaround: None Status: For the steppings affected, see the Summary Tables of Changes. R38. Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is provided since only the lower bytes change, however external logic monitoring the data transfer may be expecting an 8 byte load lock. Implication: No known commercially available chipsets are affected by this erratum. Workaround: None identified at this time. Status: For the steppings affected, see the Summary Tables of Changes. R39. Data Breakpoints on the High Half of a Floating Point Line Split May Not Be Captured Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a data breakpoint register maps to the high line of the floating point load, internal boundary conditions exist that may prevent the data breakpoint from being captured. Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 45

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
45
R37.
Using STPCLK# and Executing Code from Very Slow Memory Could Lead
to a System Hang
Problem:
The system may hang when the following conditions are met:
1.
Periodic STPCLK# mechanism is enabled via the chipset
2.
Hyper-Threading Technology is enabled
3.
One logical processor is waiting for an event (i.e. hardware interrupt)
4.
The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK# to be re-asserted.
Implication:
If this erratum occurs, the processor will go into and out of the sleep state without making
forward progress, since the logical processor will not be able to service any pending event. This
erratum has not been observed in any commercial platform running commercial software
.
Workaround:
None
Status:
For the steppings affected, see the
Summary Tables of Changes.
R38.
Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock
Problem:
When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8 byte load lock.
Implication:
No known commercially available chipsets are affected by this erratum.
Workaround:
None identified at this time.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R39.
Data Breakpoints on the High Half of a Floating Point Line Split May Not Be
Captured
Problem:
When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a
data breakpoint register maps to the
high line of the floating point load, internal boundary
conditions exist that may prevent the data breakpoint from being captured.
Implication:
When this erratum occurs, a data breakpoint will not be captured.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.