Intel SL8K2 Specification Update - Page 40

Bus Locks and SMC Detection May Cause the Processor to Hang

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Errata R R23. Bus Locks and SMC Detection May Cause the Processor to Hang Temporarily Problem: The processor may temporarily hang in a Hyper-Threading Technology enabled system if one logical processor executes a synchronization loop that includes one or more locks and is waiting for release by the other logical processor. If the releasing logical processor is executing instructions that are within the detection range of the self -modifying code (SMC) logic, then the processor may be locked in the synchronization loop until the arrival of an interrupt or other event. Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop making forward progress. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R24. PWRGOOD and TAP Signals Maximum Input Hysteresis Higher Than Specified Problem: The maximum input hysteresis for the PWRGOOD and TAP input signals are specified at 350 mV. The actual value could be as high as 800 mV. Implication: The PWRGOOD and TAP inputs may switch at different levels than previously documented specifications. Intel has not observed any issues in validation or simulation as a result of this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R25. Incorrect Physical Address Size Returned by CPUID Instruction Problem: The CPUID instruction Function 80000008H (Extended Address Sizes Function) returns the address sizes supported by the processor in the EAX register. This Function returns an incorrect physical address size value of 40 bits. The correct physical address size is 36 bits. Implication: Function 80000008H returns an incorrect physical address size value of 40 bits. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 40 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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Errata
R
40
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R23.
Bus Locks and SMC Detection May Cause the Processor to Hang
Temporarily
Problem:
The processor may temporarily hang in a Hyper-Threading Technology enabled system if one
logical processor executes a synchronization loop that includes one or more locks and is waiting
for release by the other logical processor. If the releasing logical processor is executing
instructions that are within the detection range of the self -modifying code (SMC) logic, then the
processor may be locked in the synchronization loop until the arrival of an interrupt or other
event.
Implication:
If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R24.
PWRGOOD and TAP Signals Maximum Input Hysteresis Higher Than
Specified
Problem:
The maximum input hysteresis for the PWRGOOD and TAP input signals are specified at
350 mV. The actual value could be as high as 800 mV.
Implication:
The PWRGOOD and TAP inputs may switch at different levels than previously documented
specifications. Intel has not observed any issues in validation or simulation as a result of this
erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R25.
Incorrect Physical Address Size Returned by CPUID Instruction
Problem:
The CPUID instruction Function 80000008H (Extended Address Sizes Function) returns the
address sizes supported by the processor in the EAX register. This Function returns an incorrect
physical address size value of 40 bits. The correct physical address size is 36 bits.
Implication:
Function 80000008H returns an incorrect physical address size value of 40 bits.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary
Tables of Changes.