Intel SL8K2 Specification Update - Page 41

Incorrect Debug Exception #DB May Occur When a Data Breakpoint Is Set

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Errata R R26. Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set on an FP Instruction Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain data about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a Debug Exception. Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction. Intel has not observed this erratum with any commercially available software or system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R27. xAPIC May Not Report Some Illegal Vector Errors Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive Illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received message. When an illegal vector error is received on the same internal clock that the error status register is being written (due to a previous error), bit 6 does not get set and illegal vector errors are not flagged Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same time as other xAPIC errors. The other xAPIC errors will continue to be reported. Workaround: None identified Status: For the stepping affected, see the Summary Tables of Changes. R28. Enabling No-Eviction Mode (NEM) May Prevent the Operation of the Second Logical Processor in a Hyper-Threading Technology Enabled Processor Problem: In an HT Technology enabled system, when NEM is enabled by setting bit 0 of MSR 080h (IA32_BIOS_CACHE_AS_RAM), the second logical processor may fail to wake up from "Waitfor-SIPI" state. Implication: In an HT Technology enabled system, the second logical processor may not respond to SIPI. The OS will continue to operate but with fewer logical processors than expected. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the stepping affected, see the Summary Tables of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 41

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Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
41
R26.
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set
on an FP Instruction
Problem:
The default Microcode Floating Point Event Handler routine executes a series of loads to obtain
data about the FP instruction that is causing the FP event. If a data breakpoint is set on the
instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint
resulting in a Debug Exception.
Implication:
An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction.
Intel has not observed this erratum with any commercially available software or system.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary
Tables of Changes.
R27.
xAPIC May Not Report Some Illegal Vector Errors
Problem:
The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive
Illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a
received message. When an illegal vector error is received on the same internal clock that the
error status register is being written (due to a previous error), bit 6 does not get set and illegal
vector errors are not flagged
Implication:
The xAPIC may not report some Illegal Vector errors when they occur at approximately the same
time as other xAPIC errors. The other xAPIC errors will continue to be reported
.
Workaround:
None identified
Status:
For the stepping affected, see the
Summary Tables of Changes.
R28.
Enabling No-Eviction Mode (NEM) May Prevent the Operation of the
Second Logical Processor in a Hyper-Threading Technology Enabled
Processor
Problem:
In an HT Technology enabled system, when NEM is enabled by setting bit 0 of MSR 080h
(IA32_BIOS_CACHE_AS_RAM), the second logical processor may fail to wake up from "Wait-
for-SIPI" state.
Implication:
In an HT Technology enabled system, the second logical processor may not respond to SIPI.
The
OS will continue to operate but with fewer logical processors than expected.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the stepping affected, see the
Summary Tables of Changes.