Intel SL8K2 Specification Update - Page 72

The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set

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Errata R R121. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors Occur at the Same Time Problem: When two enabled MC0/MC1 un-correctable machine check errors are detected in the same bank in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set. Implication: The highest priority error will be logged and signaled if enabled, but the overflow bit in the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R122. Debug Status Register (DR6) Breakpoint Condition Detected Flags May be set Incorrectly Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under certain boundary conditions when either: • A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger breakpoint instruction, or • Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect exception condition. Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R123. A Continuous Loop Executing Bus Lock Transactions on One Logical Processor may Prevent Another Logical Processor from Acquiring Resources Problem: In a system supporting Hyper-Threading Technology, when one hardware thread is in a continuous loop executing bus locks plus other traffic, the other hardware thread may be prevented from acquiring resources to also execute a lock. Implication: This erratum may cause system hang or unpredictable system behavior. This erratum has not been observed with commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. § 72 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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Errata
R
72
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
R121.
The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set
when Multiple Un-correctable Machine Check Errors Occur at the Same
Time
Problem:
When two enabled MC0/MC1 un-correctable machine check errors are detected in the same bank
in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS
/ IA32_MC1_STATUS register, but the overflow bit may not be set.
Implication:
The highest priority error will be logged and signaled if enabled, but the overflow bit in the
IA32_MC0_STATUS/ IA32_MC1_STATUS register may not be set.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
R122.
Debug Status Register (DR6) Breakpoint Condition Detected Flags May be
set Incorrectly
Problem:
The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under
certain boundary conditions when either:
•
A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger
breakpoint instruction, or
•
Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect
exception condition.
Implication:
Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
R123.
A Continuous Loop Executing Bus Lock Transactions on One Logical
Processor may Prevent Another Logical Processor from Acquiring
Resources
Problem:
In a system supporting Hyper-Threading Technology, when one hardware thread is in a
continuous loop executing bus locks plus other traffic, the other hardware thread may be
prevented from acquiring resources to also execute a lock.
Implication:
This erratum may cause system hang or unpredictable system behavior. This erratum has not been
observed with commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
§